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3.3V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits 2,359,296 bits
IDT72V51546 IDT72V51556
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FEATURES:
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Choose from among the following memory density options: IDT72V51546 Total Available Memory = 1,179,648 bits IDT72V51556 Total Available Memory = 2,359,296 bits Configurable from 1 to 32 Queues Queues may be configured at master reset from the pool of Total Available Memory in blocks of 256 x 36 Independent Read and Write access per queue User programmable via serial port Default multi-queue device configurations - IDT72V51546 : 1,024 x 36 x 32Q - IDT72V51556 : 2,048 x 36 x 32Q 100% Bus Utilization, Read and Write on every clock cycle 166 MHz High speed operation (6ns cycle time) 3.7ns access time Individual, Active queue flags (OV, FF, PAE, PAF, PR) 8 bit parallel flag status on both read and write ports Shows PAE and PAF status of 8 Queues
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Direct or polled operation of flag status bus Global Bus Matching - (All Queues have same Input Bus Width and Output Bus Width) User Selectable Bus Matching Options: - x36in to x36out - x18in to x36out - x9in to x36out - x36in to x18out - x36in to x9out FWFT mode of operation on read port Packet mode operation Partial Reset, clears data in single Queue Expansion of up to 8 multi-queue devices in parallel is available JTAG Functionality (Boundary Scan) Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm HIGH Performance submicron CMOS technology Industrial temperature range (-40C to +85C) is available
FUNCTIONAL BLOCK DIAGRAM
MULTI-QUEUE FLOW-CONTROL DEVICE Q0
FSTR WRADD WEN WCLK
8
READ CONTROL
WADEN
RADEN ESTR
8
WRITE CONTROL
Q1
RDADD REN RCLK OE
Q2 Din Qout
x36 DATA OUT
WRITE FLAGS READ FLAGS
OV PR PAE
8
x36 DATA IN
FF PAF PAFn
8
Q31
PAEn/PRn
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
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2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
JUNE 2003
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
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DESCRIPTION:
The IDT72V51546/72V51556 multi-queue flow-control devices are single chip within which anywhere between 1 and 32 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. Data writes and reads can be performed at high speeds up to 166MHz, with access times of 3.7ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously. The device provides Full flag and Output Valid flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full and Programmable Almost Empty flag for each queue is provided. Two 8 bit programmable flag busses are available, providing status of queues not selected for write or read operations. When 8 or less queues are configured in the device these flag busses provide an individual flag per queue, when more than 8 queues are used, either a Polled or Direct mode of bus operation provides the flag busses with all queues status. Bus Matching is available on this device, either port can be 9 bits, 18 bits or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching is used the device ensures the logical transfer of data throughput in a Little Endian manner.
A packet mode of operation is also provided when the device is configured for 36 bit input and 36 bit output port sizes. The Packet mode provides the user with a flag output indicating when at least one (or more) packets of data within a queue is available for reading. The Packet Ready provides the user with a means by which to mark the start and end of packets of data being passed through the queues. The multi-queue device then provides the user with an internally generated packet ready status per queue. The user has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 32, the individual queue depths being independent of each other. The programmable flag positions are also user programmable. All programming is done via a dedicated serial port. If the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner. Both Master Reset and Partial Reset pins are provided on this device. A Master Reset latches in all configuration setup pins and must be performed before programming of the device can take place. A Partial Reset will reset the read and write pointers of an individual queue, provided that the queue is selected on both the write port and read port at the time of partial reset. A JTAG test port is provided, here the multi-queue flow-control device has a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline of the functional blocks within the device.
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
Din x9, x18, x36 D0 - D35 WCLK WEN INPUT DEMUX 2 D35 = TEOP D34 = TSOP
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TMS JTAG Logic TDI TDO TCK TRST
WRADD WADEN
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Write Control Logic Write Pointers Packet Mode Logic
PR 8 PRn/PAEn
FSTR PAFn FSYNC FXO FXI FF PAF SI SO SCLK SENI SENO FM IW OW BM MAST PKT ID0 ID1 ID2 DF DFM PRS MRS
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PAF General Flag Monitor Upto 32 FIFO Queues Active Q Flags 2.3 Mbit Dual Port Memory
Active Q Flags
OV PAE
Serial Multi-Queue Programming
PAE General Flag Monitor
ESTR ESYNC EXI EXO
Read Pointers Reset Logic 8 Read Control Logic RDADD RADEN REN Device ID 3 Bit PAE/ PAF Offset OUTPUT REGISTER RCLK OUTPUT MUX
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Q35 = REOP Q34 = RSOP
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OE
Q0 - Q35 Qout x9, x18, x36
Figure 1. Multi-Queue Flow-Control Device Block Diagram
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
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PIN CONFIGURATION
A1 BALL PAD CORNER
A
D14 D13 D12 D10 D7 D4 D1 TCK TDO ID1 Q3 Q6 Q9 Q12 Q14 Q15
B
D15 D16 D11 D9 D6 D3 D0 TMS TDI ID0 Q2 Q5 Q8 Q11 Q13 Q19
C
D17 D18 D19 D8 D5 D2 TRST GND ID2 Q0 Q1 Q4 Q7 Q10 Q17 Q18
D
D20 D21 D22 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Q16 Q21 Q20
E
D23 D24 D25 VCC VCC VCC VCC GND GND VCC VCC VCC VCC Q24 Q23 Q22
F
D26 D27 D28 VCC VCC GND GND GND GND GND GND VCC VCC Q27 Q26 Q25
G
D29 D30 D31 VCC VCC GND GND GND GND GND GND VCC VCC Q30 Q29 Q28
H
D32 D33 D34 VCC GND GND GND GND GND GND GND GND VCC Q33 Q32 Q31
J
GND GND D35 VCC GND GND GND GND GND GND GND GND VCC PKT Q35 Q34
K
GND GND GND VCC VCC GND GND GND GND GND GND VCC VCC GND MAST FM
L
SI DFM DF VCC VCC GND GND GND GND GND GND VCC VCC BM IW OW
M
SENO SENI SO VCC VCC VCC VCC GND GND VCC VCC VCC VCC OE RDADD0 RDADD1
N
WRADD1 WRADD0 SCLK VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC RDADD2 RDADD3 RDADD4
P
WRADD4 WRADD3 WRADD2 WADEN PAF3 PAF6 PAF7 FF OV PAE PAE7 PAE6 PAE3 RDADD5 RDADD6 RDADD7
R
WRADD6 WRADD5 FSYNC FSTR PAF2 PAF5 PAF4 PAF PR DNC DNC PAE5 PAE2 RADEN ESTR ESYNC
T
WRADD7 FXI FXO PAF0 PAF1 WEN WCLK PRS MRS RCLK REN PAE4 PAE1 PAE0 EXO EXI
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NOTE: 1. DNC - Do Not Connect.
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PBGA (BB256-1, order code: BB) TOP VIEW
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
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DETAILED DESCRIPTION
MULTI-QUEUE STRUCTURE The IDT multi-queue flow-control device has a single data input port and single data output port with up to 32 FIFO queues in parallel buffering between the two ports. The user can setup between 1 and 32 Queues within the device. These queues can be configured to utilize the total available memory, providing the user with full flexibility and ability to configure the queues to be various depths, independent of one another. MEMORY ORGANIZATION/ ALLOCATION The memory is organized into what is known as "blocks", each block being 256 x36 bits. When the user is configuring the number of queues and individual queue sizes the user must allocate the memory to respective queues, in units of blocks, that is, a single queue can be made up from 0 to m blocks, where m is the total number of blocks available within a device. Also the total size of any given queue must be in increments of 256 x36. For the IDT72V51546 and IDT72V51556 the Total Available Memory is 128 and 256 blocks respectively (a block being 256 x36). Queues can be built from these blocks to make any size queue desired and any number of queues desired. BUS WIDTHS The input port is common to all queues within the device, as is the output port. The device provides the user with Bus Matching options such that the input port and output port can be either x9, x18 or x36 bits wide provided that at least one of the ports is x36 bits wide, the read and write port widths being set independently of one another. Because the ports are common to all queues the width of the queues is not individually set, so that the input width of all queues are equal and the output width of all queues are equal. WRITING TO & READING FROM THE MULTI-QUEUE Data being written into the device via the input port is directed to a discrete queue via the write queue select address inputs. Conversely, data being read from the device read port is read from a queue selected via the read queue select address inputs. Data can be simultaneously written into and read from the same queue or different queues. Once a queue is selected for data writes or reads, the writing and reading operation is performed in the same manner as a conventional IDT synchronous FIFO, utilizing clocks and enables, there is a single clock and enable per port. When a specific queue is addressed on the write port, data placed on the data inputs is written to that queue sequentially based on the rising edge of a write clock provided setup and hold times are met. Conversely, data is read on to the output port after an access time from a rising edge on a read clock. The operation of the write port is comparable to the function of a conventional FIFO operating in standard IDT mode. Write operations can be performed on the write port provided that the queue currently selected is not full, a full flag output provides status of the selected queue. The operation of the read port is comparable to the function of a conventional FIFO operating in FWFT mode. When a queue is selected on the output port, the next word in that queue will automatically fall through to the output register. All subsequent words from that queue require an enabled read cycle. Data cannot be read from a selected queue if that queue is empty, the read port provides an Output Valid flag indicating when data read out is valid. If the user switches to a queue that is empty, the last word from the previous queue will remain on the output register. As mentioned, the write port has a full flag, providing full status of the selected queue. Along with the full flag a dedicated almost full flag is provided, this almost full flag is similar to the almost full flag of a conventional IDT FIFO. The device provides a user programmable almost full flag for all 32 queues and when a
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respective queue is selected on the write port, the almost full flag provides status for that queue. Conversely, the read port has an output valid flag, providing status of the data being read from the queue selected on the read port. As well as the output valid flag the device provides a dedicated almost empty flag. This almost empty flag is similar to the almost empty flag of a conventional IDT FIFO. The device provides a user programmable almost empty flag for all 32 queues and when a respective queue is selected on the read port, the almost empty flag provides status for that queue. PROGRAMMABLE FLAG BUSSES In addition to these dedicated flags, full & almost full on the write port and output valid & almost empty on the read port, there are two flag status busses. An almost full flag status bus is provided, this bus is 8 bits wide. Also, an almost empty flag status bus is provided, again this bus is 8 bits wide. The purpose of these flag busses is to provide the user with a means by which to monitor the data levels within queues that may not be selected on the write or read port. As mentioned, the device provides almost full and almost empty registers (programmable by the user) for each of the 32 queues in the device. In the IDT72V51546/72V51556 multi-queue flow-control devices the user has the option of utilizing anywhere between 1 and 32 queues, therefore the 8 bit flag status busses are multiplexed between the 32 queues, a flag bus can only provide status for 8 of the 32 queues at any moment, this is referred to as a "Quadrant", such that when the bus is providing status of queues 1 through 8, this is quadrant 1, when it is queues 9 through 16, this is quadrant 2 and so on up to quadrant 4. If less than 32 queues are setup in the device, there are still 4 quadrants, such that in "Polled" mode of operation the flag bus will still cycle through 4 quadrants. If for example only 22 queues are setup, quadrants 1 and 2 will reflect status of queues 1 through 8 and 9 through 16 respectively. Quadrant 3 will reflect the status of queues 17 through 22 on the least significant 6 bits, the most significant 2 bits of the flag bus are don't care and the 4th quadrant outputs will be don't care also. The flag busses are available in two user selectable modes of operation, "Polled" or "Direct". When operating in polled mode a flag bus provides status of each quadrant sequentially, that is, on each rising edge of a clock the flag bus is updated to show the status of each quadrant in order. The rising edge of the write clock will update the almost full bus and a rising edge on the read clock will update the almost empty bus. The mode of operation is always the same for both the almost full and almost empty flag busses. When operating in direct mode, the quadrant on the flag bus is selected by the user. So the user can actually address the quadrant to be placed on the flag status busses, these flag busses operate independently of one another. Addressing of the almost full flag bus is done via the write port and addressing of the almost empty flag bus is done via the read port. PACKET MODE The multi-queue flow-control device also offers a "Packet Mode" operation. Packet Mode is user selectable and requires the device to be configured with both write and read ports as 36 bits wide. In packet mode, users can define the length of packets or frame by using the two most significant bits of the 36bit word. Bit 34 is used to mark the Start of Packet (SOP) and bit 35 is used to mark the End of Packet (EOP) as shown in Table 5). When writing data into a given queue, the first word being written is marked, by the user setting bit 34 as the "Start of Packet" (SOP) and the last word written is marked as the "End of Packet" (EOP) with all words written between the Start of Packet (SOP) marker (bit 34) and the End of packet (EOP) packet marker (bit 35) constituting the entire packet. A packet can be any length the user desires, up to the total available memory in the multi-queue flow-control device. The device monitors the SOP (bit 34) and looks for the word that contains the EOP (bit 35). The read
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
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port is supplied with an additional status flag, "Packet Ready". The Packet Ready (PR) flag in conjunction with Output Valid (OV) indicates when at least one packet is available to read. When in packet mode the almost empty flag status, provides packet ready flag status for individual queues. EXPANSION Expansion of multi-queue devices is also possible, up to 8 devices can be connected in a parallel fashion providing the possibility of both depth expansion or queue expansion. Depth Expansion means expanding the depths of individual queues. Queue expansion means increasing the total number of queues available. Depth expansion is possible by virtue of the fact that more
memory blocks within a multi-queue device can be allocated to increase the depth of a queue. For example, depth expansion of 8 devices provides the possibility of 8 queues of 64K x36 deep, each queue being setup within a single device utilizing all memory blocks available to produce a single queue. This is the deepest queue that can setup within a device. For queue expansion a maximum number of 256 (8 x 32) queues may be setup, each queue being 2K x36 deep, if less queues are setup, then more memory blocks will be available to increase queue depths if desired. When connecting multi-queue devices in expansion mode all respective input pins (data & control) and output pins (data & flags), should be "connected" together between individual devices.
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
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PIN DESCRIPTIONS
Symbol & Pin No. BM (L14) Name Bus Matching I/O TYPE LVTTL INPUT LVTTL INPUT Description This pin is setup before Master Reset and must not toggle during any device operation. This pin is used along with IW and OW to setup the multi-queue flow-control device bus width. Please refer to Table 3 for details. These are the 36 data input pins. Data is written into the device via these input pins on the rising edge of WCLK provided that WEN is LOW. Note, that in Packet mode D32-D35 may be used as packet markers, please see packet ready functional discussion for more detail. Due to bus matching not all inputs may be used, any unused inputs should be tied LOW. If the user requires default programming of the multi-queue device, this pin must be setup before Master Reset and must not toggle during any device operation. The state of this input at master reset determines the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128. The multi-queue device requires programming after master reset. The user can do this serially via the serial port, or the user can use the default method. If DFM is LOW at master reset then serial mode will be selected, if HIGH then default mode is selected. If direct operation of the PAEn bus has been selected, the ESTR input is used in conjunction with RCLK and the RDADD bus to select a quadrant of queues to be placed on to the PAEn bus outputs. A quadrant addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If Polled operations has been selected, ESTR should be tied inactive, LOW. Note, that a PAEn flag bus selection cannot be made, (ESTR must NOT go active) until programming of the part has been completed and SENO has gone LOW.
D[35:0] Data Input Bus Din (See Pin No. table for details) DF(1) (L3) DFM(1) (L2) ESTR (R15) Default Flag
LVTTL INPUT LVTTL INPUT LVTTL INPUT
Default Mode
PAEn Flag Bus Strobe
ESYNC (R16)
PAEn Bus Sync
LVTTL ESYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAEn bus OUTPUT during Polled operation of the PAEn bus. During Polled operation each quadrant of queue status flags is loaded on to the PAEn bus outputs sequentially based on RCLK. The first RCLK rising edge loads quadrant 1 on to PAEn, the second RCLK rising edge loads quadrant 2 and so on. The fifth RCLK rising edge will again load quadrant 1. During the RCLK cycle that quadrant 1 of a selected device is placed on to the PAEn bus, the ESYNC output will be HIGH. For all other quadrants of that device, the ESYNC output will be LOW. LVTTL INPUT The EXI input is used when multi-queue devices are connected in expansion mode and Polled PAEn bus operation has been selected. EXI of device `N' connects directly to EXO of device `N-1'. The EXI receives a token from the previous device in a chain. In single device mode the EXI input must be tied LOW if the PAEn bus is operated in direct mode. If the PAEn bus is operated in polled mode the EXI input must be connected to the EXO output of the same device. In expansion mode the EXI of the first device should be tied LOW, when direct mode is selected.
EXI (T16)
PAEn Bus Expansion In
EXO (T15)
PAEn Bus Expansion Out
LVTTL EXO is an output that is used when multi-queue devices are connected in expansion mode and Polled OUTPUT PAEn bus operation has been selected . EXO of device `N' connects directly to EXI of device `N+1'. This pin pulses when device N has placed its final (4th) quadrant on to the PAEn bus with respect to RCLK. This pulse (token) is then passed on to the next device in the chain `N+1' and on the next RCLK rising edge the first quadrant of device N+1 will be loaded on to the PAEn bus. This continues through the chain and EXO of the last device is then looped back to EXI of the first device. The ESYNC output of each device in the chain provides synchronization to the user of this looping event. LVTTL OUTPUT This pin provides the full flag output for the active queue, that is, the queue selected on the input port for write operations, (selected via WCLK, WRADD bus and WADEN). On the WCLK cycle after a queue selection, this flag will show the status of the newly selected queue. Data can be written to this queue on the next cycle provided FF is HIGH. This flag has High-Impedance capability, this is important during expansion of devices, when the FF flag output of up to 8 devices may be connected together on a common line. The device with a queue selected takes control of the FF bus, all other devices place their FF output into High-Impedance. When a queue selection is made on the write port this output will switch from High-Impedance control on the next WCLK cycle. This flag is synchronized to WCLK. This pin is setup before a master reset and must not toggle during any device operation. The state of the FM pin during Master Reset will determine whether the PAFn and PAEn flag busses operate in either Polled or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct.
FF (P8)
Full Flag
FM(1) (K16)
Flag Mode
LVTTL INPUT
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
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PIN DESCRIPTIONS (CONTINUED)
Symbol & Pin No. FSTR (R4) Name PAFn Flag Bus Strobe I/O TYPE LVTTL INPUT Description If direct operation of the PAFn bus has been selected, the FSTR input is used in conjunction with WCLK and the WRADD bus to select a quadrant of queues to be placed on to the PAFn bus outputs. A quadrant addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If Polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a PAFn flag bus selection cannot be made, (FSTR must NOT go active) until programming of the part has been completed and SENO has gone LOW.
FSYNC (R3)
PAFn Bus Sync
LVTTL FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAFn bus OUTPUT during Polled operation of the PAFn bus. During Polled operation each quadrant of queue status flags is loaded on to the PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads quadrant 1 on to PAFn, the second WCLK rising edge loads quadrant 2 and so on. The fifth WCLK rising edge will again load quadrant 1. During the WCLK cycle that quadrant 1 of a selected device is placed on to the PAFn bus, the FSYNC output will be HIGH. For all other quadrants of that device, the FSYNC output will be LOW. LVTTL INPUT The FXI input is used when multi-queue devices are connected in expansion mode and Polled PAFn bus operation has been selected . FXI of device `N' connects directly to FXO of device `N-1'. The FXI receives a token from the previous device in a chain. In single device mode the FXI input must be tied LOW if the PAFn bus is operated in direct mode. If the PAFn bus is operated in polled mode the FXI input must be connected to the FXO output of the same device. In expansion mode the FXI of the first device should be tied LOW, when direct mode is selected.
FXI (T2)
PAFn Bus Expansion In
FXO (T3)
PAFn Bus Expansion Out
LVTTL FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled OUTPUT PAFn bus operation has been selected . FXO of device `N' connects directly to FXI of device `N+1'. This pin pulses when device N has placed its final (4th) quadrant on to the PAFn bus with respect to WCLK. This pulse (token) is then passed on to the next device in the chain `N+1' and on the next WCLK rising edge the first quadrant of device N+1 will be loaded on to the PAFn bus. This continues through the chain and FXO of the last device is then looped back to FXI of the first device. The FSYNC output of each device in the chain provides synchronization to the user of this looping event. LVTTL INPUT For the 32Q multi-queue device the WRADD and RDADD address busses are 8 bits wide. When a queue selection takes place the 3 MSb's of this 8 bit address bus are used to address the specific device (the 5 LSb's are used to address the queue within that device). During write/read operations the 3 MSb's of the address are compared to the device ID pins. The first device in a chain of multi-queue's (connected in expansion mode), may be setup as `000', the second as `001' and so on through to device 8 which is `111', however the ID does not have to match the device order. In single device mode these pins should be setup as `000' and the 3 MSb's of the WRADD and RDADD address busses should be tied LOW. The ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during any device operation. Note, the device selected as the `Master' does not have to have the ID of `000'. This pin is used in conjunction with OW and BM to setup the input and output bus widths to be a combination of x9, x18 or x36, (providing that one port is x36). The state of this input at Master Reset determines whether a given device (within a chain of devices), is the Master device or a Slave. If this pin is HIGH, the device is the master if it is LOW then it is a Slave. The master device is the first to take control of all outputs after a master reset, all slave devices go to High-Impedance, preventing bus contention. If a multi-queue device is being used in single device mode, this pin must be set HIGH. A master reset is performed by taking MRS from HIGH to LOW, to HIGH. Device programming is required after master reset. The Output enable signal is an Asynchronous signal used to provide three-state control of the multi-queue data output bus, Qout. If a device has been configured as a "Master" device, the Qout data outputs will be in a Low Impedance condition if the OE input is LOW. If OE is HIGH then the Qout data outputs will be in High Impedance. If a device is configured a "Slave" device, then the Qout data outputs will always be in High Impedance until that device has been selected on the Read Port, at which point OE provides threestate of that respective device.
ID[2:0](1) (ID2-C9 ID1-A10 ID0-B10)
Device ID Pins
IW(1) (L15) MAST(1) (K15)
Input Width Master Device
LVTTL INPUT LVTTL INPUT
MRS (T9) OE (M14)
Master Reset Output Enable
LVTTL INPUT LVTTL INPUT
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
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PIN DESCRIPTIONS (CONTINUED)
Symbol & Pin No. OV (P9) Name Output Valid Flag I/O TYPE Description LVTTL This output flag provides output valid status for the data word present on the multi-queue flow-control OUTPUT device data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That is, there is a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time the OV flag represents the data in that respective queue. When a selected queue on the read port is read to empty, the OV flag will go HIGH, indicating that data on the output bus is not valid. The OV flag also has High-Impedance capability, required when multiple devices are used and the OV flags are tied together. LVTTL INPUT This pin is setup during Master Reset and must not toggle during any device operation. This pin is used in conjunction with IW and BM to setup the data input and output bus widths to be a combination of x9, x18 or x36, (providing that one port is x36).
OW(1) (L16) PAE (P10)
Output Width
Programmable LVTTL This pin provides the Almost-Empty flag status for the queue that has been selected on the output port Almost-Empty Flag OUTPUT for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is synchronized to RCLK.
PAEn/PRn Programmable LVTTL On the 32Q device the PAEn/ PRn bus is 8 bits wide. During a Master Reset this bus is setup for either (See Pin No. Almost-Empty Flag OUTPUT Almost Empty mode or Packet mode. This output bus provides PAE/ PRn status of 8 queues (1 quadrant), table for details) Bus/Packet Ready within a selected device, having a total of 4 quadrants. During Queue read/write operations these outputs Flag Bus provide programmable empty flag status or packet ready status, in either direct or polled mode. The mode of flag operation is determined during master reset via the state of the FM input. This flag bus is capable of High-Impedance state, this is important during expansion of multi-queue devices. During direct operation the PAEn/PRn bus is updated to show the PAE/PR status of a quadrant of queues within a selected device. Selection is made using RCLK, ESTR and RDADD. During Polled operation the PAEn/PRn bus is loaded with the PAE/ PRn status of multi-queue flow-control quadrants sequentially based on the rising edge of RCLK. PAE or PR operation is determined by the state of PKT during master reset. PAF (R8) Programmable Almost-Full Flag LVTTL This pin provides the Almost-Full flag status for the queue that has been selected on the input port for write OUTPUT operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected queue is almost-full. This flag output may be duplicated on one of the PAFn bus lines. This flag is synchronized to WCLK. LVTTL On the 32Q device the PAFn bus is 8 bits wide. At any one time this output bus provides PAF status of OUTPUT 8 queues (1 quadrant), within a selected device, having a total of 4 quadrants. During Queue read/write operations these outputs provide programmable full flag status, in either direct or polled mode. The mode of flag operation is determined during master reset via the state of the FM input. This flag bus is capable of High-Impedance state, this is important during expansion of multi-queue devices. During direct operation the PAFn bus is updated to show the PAF status of a quadrant of queues within a selected device. Selection is made using WCLK, FSTR, WRADD and WADEN. During Polled operation the PAFn bus is loaded with the PAF status of multi-queue flow-control quadrants sequentially based on the rising edge of WCLK. LVTTL INPUT The state of this pin during a Master Reset will determine whether the part is operating in Packet mode providing both a Packet Ready (PR) output and a Programmable Almost Empty (PAE) discrete output, or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part will operate in packet mode, if it is LOW then almost empty mode. If packet mode has been selected the read port flag bus becomes packet ready flag bus, PRn and the discrete packet ready flag, PR is functional. If almost empty operation has been selected then the flag bus provides almost empty status, PAEn and the discrete almost empty flag, PAE is functional, the PR flag is inactive and should not be connected. Packet Ready utilizes user marked locations to identify start and end of packets being written into the device. Packet Mode can only be selected if both the input port width and output port width are 36 bits.
PAFn Programmable (See Pin No. Almost-Full Flag table for details) Bus
PKT(1) (J14)
Packet Mode
PR (R9)
Packet Ready Flag
LVTTL If packet mode has been selected this flag output provides Packet Ready status of the queue selected OUTPUT for read operations. During a master reset the state of the PKT input determines whether Packet mode of operation will be used. If Packet mode is selected, then the condition of the PR flag and OV signal are asserted indicates a packet is ready for reading. The user must mark the start of a packet and the end of a packet when writing data into a queue. Using these Start Of Packet (SOP) and End Of Packet (EOP) markers, the multi-queue device sets PR LOW if one or more "complete" packets are available in the queue. A complete packet(s) must be written before the user is allowed to switch queues.
9
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol & Pin No. PRS (T8) Name Partial Reset I/O TYPE LVTTL INPUT Description A Partial Reset can be performed on a single queue selected within the multi-queue device. Before a Partial Reset can be performed on a queue, that queue must be selected on both the write port and read port 2 clock cycles before the reset is performed. A Partial Reset is then performed by taking PRS LOW for one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to the first memory location, none of the devices configuration will be changed.
Q[35:0] Data Output Bus Qout (See Pin No. table for details) RADEN (R14) Read Address Enable
LVTTL These are the 36 data output pins. Data is read out of the device via these output pins on the rising edge OUTPUT of RCLK provided that REN is LOW, OE is LOW and the queue is selected. Note, that in Packet mode Q32-Q35 may be used as packet markers, please see packet ready functional discussion for more detail. Due to bus matching not all outputs may be used, any unused outputs should not be connected. LVTTL INPUT The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note, that a read queue selection cannot be made, (RADEN must NOT go active) until programming of the part has been completed and SENO has gone LOW. When enabled by REN, the rising edge of RCLK reads data from the selected queue via the output bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the PAEn/PRn flag quadrant to be placed on the PAEn/PRn bus during direct flag operation. During polled flag operation the PAEn/PRn bus is cycled with respect to RCLK and the ESYNC signal is synchronized to RCLK. The PAE, PR and OV outputs are all synchronized to RCLK. During device expansion the EXO and EXI signals are based on RCLK. RCLK must be continuous and free-running. For the 32Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The first function of RDADD is to select a queue to be read from. The least significant 5 bits of the bus, RDADD[4:0] are used to address 1 of 32 possible queues within a multi-queue device. The most significant 3 bits, RDADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. These 3 MSB's will address a device with the matching ID code. The address present on the RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that data can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge). On the next rising RCLK edge after a read queue select, a data word from the previous queue will be placed onto the outputs, Qout, regardless of the REN input. Two RCLK rising edges after read queue select, data will be placed on to the Qout outputs from the newly selected queue, regardless of REN due to the first word fall through effect. The second function of the RDADD bus is to select the quadrant of queues to be loaded on to the PAEn/PRn bus during strobed flag mode. The least significant 2 bits, RDADD[1:0] are used to select the quadrant of a device to be placed on the PAEn bus. The most significant 3 bits, RDADD[7:5] are again used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. Address bits RDADD[4:2] are don't care during quadrant selection. The quadrant address present on the RDADD bus will be selected on the rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge). Please refer to Table 2 for details on RDADD bus. The REN input enables read operations from a selected queue based on a rising edge of RCLK. A queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless of the state of REN. Data from a newly selected queue will be available on the Qout output bus on the second RCLK cycle after queue selection regardless of REN due to the FWFT operation. A read enable is not required to cycle the PAEn/PRn bus (in polled mode) or to select the PAEn quadrant , (in direct mode). If serial programming of the multi-queue device has been selected during master reset, the SCLK input clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device on the rising edge of SCLK provided that SENI is enabled, LOW. When expansion of devices is performed the SCLK of all devices should be connected to the same source. During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the part (via a rising edge of SCLK), provided the SENI input of that device is LOW. If multiple devices are
10
RCLK (T10)
Read Clock
LVTTL INPUT
RDADD Read Address Bus [7:0] (RDADD7-P16 RDADD6-P15 RDADD5-P14 RDADD4-N16 RDADD3-N15 RDADD2-N14 RDADD1-M16 RDADD0-M15)
LVTTL INPUT
REN (T11)
Read Enable
LVTTL INPUT
SCLK (N3)
Serial Clock
LVTTL INPUT
SENI (M2)
Serial Input Enable
LVTTL INPUT
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol & Pin No. SENI (Continued) (M2) SENO (M1) Name Serial Input Enable I/O TYPE LVTTL INPUT Description cascaded, the SENI input should be connected to the SENO output of the previous device. So when serial loading of a given device is complete, its SENO output goes LOW, allowing the next device in the chain to be programmed (SENO will follow SENI of a given device once that device is programmed). The SENI input of the master device (or single device), should be controlled by the user.
Serial Output Enable
LVTTL This output is used to indicate that serial programming or default programming of the multi-queue device OUTPUT has been completed. SENO follows SENI once programming of a device is complete. Therefore, SENO will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENO wil also go HIGH. When the SENO output goes LOW, the device is ready to begin normal read/write operations. If multiple devices are cascaded and serial programming of the devices will be used, the SENO output should be connected to the SENI input of the next device in the chain. When serial programming of the first device is complete, SENO will go LOW, thereby taking the SENI input of the next device LOW and so on throughout the chain. When a given device in the chain is fully programmed the SENO output essentially follows the SENI input. The user should monitor the SENO output of the final device in the chain. When this output goes LOW, serial loading of all devices has been completed. LVTTL INPUT During serial programming this pin is loaded with the serial data that will configure the multi-queue devices. Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion mode the serial data input is loaded into the first device in a chain. When that device is loaded and its SENO has gone LOW, the data present on SI will be directly output to the SO output. The SO pin of the first device connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
SI (L1)
Serial In
SO (M3) TCK(2) (A8)
Serial Out
LVTTL This output is used in expansion mode and allows serial data to be passed through devices in the chain OUTPUT to complete programming of all devices. The SI of a device connects to SO of the previous device in the chain. The SO of the final device in a chain should not be connected. LVTTL INPUT Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needsto be tied to GND. One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
JTAG Clock
TDI(2) (B9) TDO(2) (A9)
JTAG Test Data Input JTAG Test Data Output
LVTTL INPUT
LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan OUTPUT operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states. LVTTL INPUT LVTTL INPUT TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected. TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the JTAG function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An internal pull-up resistor forces TRST HIGH if left unconnected. The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue change cycle(s). WADEN should not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note, that a write queue selection cannot be made, (WADEN must NOT go active) until programming of the part has been completed and SENO has gone LOW. When enabled by WEN, the rising edge of WCLK writes data into the selected queue via the input bus, Din. The queue to be written to is selected via the WRADD address bus and a rising edge of WCLK while WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also select the flag quadrant to be placed on the PAFn bus during direct flag operation. During polled flag operation the PAFn
11
TMS(2) (B8) TRST(2) (C7)
JTAG Mode Select JTAG Reset
WADEN (P4)
Write Address Enable
LVTTL INPUT
WCLK (T7)
Write Clock
LVTTL INPUT
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol & Pin No. WCLK (Continued) (T7) WEN (T6) Name Write Clock I/O TYPE LVTTL INPUT LVTTL INPUT Description bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK. The PAFn, PAF and FF outputs are all synchronized to WCLK. During device expansion the FXO and FXI signals are based on WCLK. The WCLK must be continuous and free-running. The WEN input enables write operations to a selected queue based on a rising edge of WCLK. A queue to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless of the state of WEN. Data present on Din can be written to a newly selected queue on the second WCLK cycle after queue selection provided that WEN is LOW. A write enable is not required to cycle the PAFn bus (in polled mode) or to select the PAFn quadrant , (in direct mode). For the 32Q device the WRADD bus is 8 bits. The WRADD bus is a dual purpose address bus. The first function of WRADD is to select a queue to be written to. The least significant 5 bits of the bus, WRADD[4:0] are used to address 1 of 32 possible queues within a multi-queue device. The most significant 3 bits, WRADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. These 3 MSB's will address a device with the matching ID code. The address present on the WRADD bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that data present on the Din bus can be written into the previously selected queue on this WCLK edge and on the next rising WCLK also, providing that WEN is LOW). Two WCLK rising edges after write queue select, data can be written into the newly selected queue. The second function of the WRADD bus is to select the quadrant of queues to be loaded on to the PAFn bus during strobed flag mode. The least significant 2 bits, WRADD[1:0] are used to select the quadrant of a device to be placed on the PAFn bus. The most significant 3 bits, WRADD[7:5] are again used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. Address bits WRADD[4:2] are don't care during quadrant selection. The quadrant address present on the WRADD bus will be selected on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be written into the previously selected queue on this WCLK edge). Please refer to Table 1 for details on the WRADD bus. These are VCC power supply pins and must all be connected to a +3.3V supply rail. These are Ground pins and must all be connected to the GND supply rail.
Write Enable
WRADD Write Address Bus [7:0] (WRADD7-T1 WRADD6-R1 WRADD5-R2 WRADD4-P1 WRADD3-P2 WRADD2-P3 WRADD1-N1 WRADD0-N2)
LVTTL INPUT
VCC (See below) GND (See below)
+3.3V Supply Ground Pin
Power Ground
NOTES: 1. Inputs should not change after Master Reset. 2. These pins are for the JTAG port. Please refer to pages 53-57 and Figures 33-35.
PIN NUMBER TABLE
Symbol D[35:0] Din Name Data Input Bus I/O TYPE LVTTL INPUT Pin Number D35-J3, D(34-32)-H(3-1), D(31-29)-G(3-1), D(28-26)-F(3-1), D(25-23)-E(3-1), D(22-20)-D(3-1), D(19-17)-C(3-1), D(16,15)-B(2,1), D(14-12)-A(1-3), D11-B3, D10-A4, D9-B4, D8-C4, D7-A5, D6-B5, D5-C5, D4-A6, D3-B6, D2-C6, D1-A7, D0-B7
PAEn/PRn Programmable AlmostEmpty Flag Bus/Packet Ready Flag Bus PAFn Q[35:0] Qout Programmable AlmostFull Flag Bus Data Output Bus
LVTTL PAE7-P11, PAE6-P12, PAE5-R12, PAE4-T12, PAE3-P13, PAE2-R13, PAE1-T13, PAE0-T14 OUTPUT LVTTL PAF7-P7, PAF6-P6, PAF5-R6, PAF4-R7, PAF3-P5, PAF2-R5, PAF1-T5, PAF0-T4 OUTPUT LVTTL Q(35,34)-J(15,16), Q(33-31)-H(14-16), Q(30-28)-G(14-16), Q(27-25)-F(14-16), Q(24-22)-E(14-16), OUTPUT Q(21,20)-D(15,16), Q19-B16, Q(18,17)-C(16,15), Q16-D14, Q(15,14)-A(16,15), Q13-B15, Q12-A14, Q11-B14, Q10-C14, Q9-A13, Q8-B13, Q7-C13, Q6-A12, Q5-B12, Q4-C12, Q3-A11, Q2-B11, Q(1,0)-C(11,10) Power Ground D(4-13), E(4-7,10-13), F(4,5,12,13), G(4,5,12,13), H(4,13), J(4,13), K(4,5,12,13), L(4,5,12,13), M(4-7,10-13), N(4-13) C8, E(8-9), F(6-11), G(6-11), H(5-12), J(1,2,5-12), K(1-3,14,6-11), L(6-11), M(8-9) R(10,11)
12
VCC GND DNC
+3.3V Supply Ground Pin Do Not Connect
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM TSTG IOUT Rating Terminal Voltage with respect to GND Storage Temperature DC Output Current Com'l & Ind'l -0.5 to +4.5 -55 to +125 -50 to +50 Unit V
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC(1) GND VIH VIL TA TA Parameter Supply Voltage (Com'l/Ind'l) Supply Voltage (Com'l/Ind'l) Input High Voltage (Com'l/Ind'l) Input Low Voltage (Com'l/Ind'l) Operating Temperature Commercial Operating Temperature Industrial Min. 3.15 0 2.0 -- 0 -40 Typ. 3.3 0 -- -- -- -- Max. 3.45 0 VCC+0.3 0.8 +70 +85 Unit V V V V
C
mA
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
C C
NOTE: 1. VCC = 3.3V 0.15V, JEDEC JESD8-A compliant.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V 0.15V, TA = 0C to +70C;Industrial: VCC = 3.3V 0.15V, TA = 40C to +85C; JEDEC JESD8-A compliant)
Symbol ILI(1) ILO(2) VOH VOL ICC1(3,4,5) ICC2(3,6) Parameter Input Leakage Current Output Leakage Current Output Logic "1" Voltage, IOH = -8 mA Output Logic "0" Voltage, IOL = 8 mA Active Power Supply Current Standby Current Min. -10 -10 2.4 -- -- -- Max. 10 10 -- 0.4 100 25 Unit A A V V mA mA
NOTES: 1. Measurements with 0.4 VIN VCC. 2. OE VIH, 0.4 VOUT VCC. 3. Tested with outputs open (IOUT = 0). 4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 5. Typical ICC1 = 16 + 3.14*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF). 6. RCLK and WCLK, toggle at 20 MHz. The following inputs should be pulled to GND: WRADD, RDADD, WADEN, RADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs. The following inputs should be pulled to VCC: WEN, REN, SENI, PRS, MRS, TDI, TMS and TRST. All other inputs are don't care, and should be pulled HIGH or LOW.
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN
(2)
Parameter(1) Input Capacitance Output Capacitance
Conditions VIN = 0V VOUT = 0V
Max. 10 10
Unit pF pF
COUT(1,2)
NOTES: 1. With output deselected, (OE VIH). 2. Characterized values, not currently tested.
13
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TEST LOADS
6 5
tCD (Typical, ns)
VCC/2 50 I/O Z0 = 50
4 3 2 1 20 30 50 80 100 Capacitance (pF) 200
5904 drw04a
5904 drw04
Figure 2a. AC Test Load
Figure 2b. Lumped Capacitive Load, Typical Derating
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 1.5ns 1.5V 1.5V See Figure 2a & 2b
OUTPUT ENABLE & DISABLE TIMING
Output Enable OE VIL Output Disable VIH
tOE & tOLZ Output Normally LOW VCC/2
100mV
tOHZ VCC/2 VOL
100mV
Output Normally HIGH
100mV
VOH
100mV
VCC/2
VCC/2
5904 drw04b
14
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V 0.15V, TA = 0C to +70C;Industrial: VCC = 3.3V 0.15V, TA = 40C to +85C; JEDEC JESD8-A compliant)
Commercial IDT72V51546L6 IDT72V51556L6 Min. Max. -- 0.6 6 2.7 2.7 2 0.5 2 0.5 10 15 10 2.0 0.5 0.6 0.6 0.6 -- 100 45 45 20 1.2 20 1.2 -- -- 1.5 1.5 20 20 2.5 1 -- -- 2 0.5 2 0.5 0.6 0.6 0.6 0.6 166 3.7 -- -- -- -- -- -- -- -- -- -- -- -- 3.7 3.7 3.7 10 -- -- -- -- -- -- -- 20 20 3.7 3.7 -- -- -- -- 3.7 3.7 -- -- -- -- 3.7 3.7 3.7 3.7 Com'l & Ind'l(1) IDT72V51546L7-5 IDT72V51556L7-5 Min. Max. -- 0.6 7.5 3.5 3.5 2.0 0.5 2.0 0.5 10 15 10 2.5 0.5 0.6 0.6 0.6 -- 100 45 45 20 1.2 20 1.2 -- -- 1.5 1.5 20 20 3.0 1 -- -- 2 0.5 2.5 0.5 0.6 0.6 0.6 0.6 133 4 -- -- -- -- -- -- -- -- -- -- -- -- 4 4 4 10 -- -- -- -- -- -- -- 20 20 4 4 -- -- -- 5 5 -- -- -- -- 4 4 4 4
Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tPRSS tPRSH tOLZ (OE-Qn)(2) tOHZ(2) tOE fC tSCLK tSCKH tSCKL tSDS tSDH tSENS tSENH tSDO tSENO tSDOP tSENOP tPCWQ tPCRQ tAS tAH tWFF tROV tSTS tSTH tQS tQH tWAF tRAE tPAF tPAE
Parameter Clock Cycle Frequency (WCLK & RCLK) Data Access Time Clock Cycle Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Reset Pulse Width Reset Setup Time Reset Recovery Time Partial Reset Setup Partial Reset Hold Output Enable to Output in Low-Impedance Output Enable to Output in High-Impedance Output Enable to Data Output Valid Clock Cycle Frequency (SCLK) Serial Clock Cycle Serial Clock High Serial Clock Low Serial Data In Setup Serial Data In Hold Serial Enable Setup Serial Enable Hold SCLK to Serial Data Out SCLK to Serial Enable Out Serial Data Out Propagation Delay Serial Enable Propagation Delay Programming Complete to Write Queue Selection Programming Complete to Read Queue Selection Address Setup Address Hold Write Clock to Full Flag Read Clock to Output Valid Strobe Setup Strobe Hold Queue Setup Queue Hold WCLK to PAF flag RCLK to PAE flag Write Clock to Synchronous Almost-Full Flag Bus Read Clock to Synchronous Almost-Empty Flag Bus
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order. 2. Values guaranteed by design, not currently tested.
15
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
(Commercial: VCC = 3.3V 0.15V, TA = 0C to +70C;Industrial: VCC = 3.3V 0.15V, TA = 40C to +85C; JEDEC JESD8-A compliant)
Commercial IDT72V51546L6 IDT72V51556L6 Min. Max. 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 4.5 6 6 6 10 1.0 0.5 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 -- -- -- -- -- -- -- Com'l & Ind'l(1) IDT72V51546L7-5 IDT72V51556L7-5 Min. Max. 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 5.75 7.5 7.5 7.5 12 1.3 0.5 4 4 4 4 4 4 4 4 4 4 4 4 4 -- -- -- -- -- -- --
Symbol tPAELZ(2) tPAEHZ(2) tPAFLZ(2) tPAFHZ(2) tFFHZ(2) tFFLZ(2) tOVLZ(2) tOVHZ(2) tFSYNC tFXO tESYNC tEXO tPR tSKEW1 tSKEW2 tSKEW3 . tSKEW4 tSKEW5 tXIS tXIH
Parameter RCLK to PAE Flag Bus to Low-Impedance RCLK to PAE Flag Bus to High-Impedance WCLK to PAF Flag Bus to Low-Impedance WCLK to PAF Flag Bus to High-Impedance WCLK to Full Flag to High-Impedance WCLK to Full Flag to Low-Impedance RCLK to Output Valid Flag to Low-Impedance RCLK to Output Valid Flag to High-Impedance WCLK to PAF Bus Sync to Output WCLK to PAF Bus Expansion to Output RCLK to PAE Bus Sync to Output RCLK to PAE Bus Expansion to Output RCLK to Packet Ready Flag SKEW time between RCLK and WCLK for FF and OV SKEW time between RCLK and WCLK for PAF and PAE SKEW time between RCLK and WCLK for PAF[0:7] and PAE[0:7] SKEW time between RCLK and WCLK for PR and OV SKEW time between RCLK and WCLK for OV when in Packet Mode Expansion Input Setup Expansion Input Hold
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order. 2. Values guaranteed by design, not currently tested.
16
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
MASTER RESET A Master Reset is performed by toggling the MRS input from HIGH to LOW to HIGH. During a master reset all internal multi-queue device setup and control registers are initialized and require programming either serially by the user via the serial port, or using the default settings. During a master reset the state of the following inputs determine the functionality of the part, these pins should be held HIGH or LOW. PKT - Packet Mode FM - Flag bus Mode IW, OW, BM - Bus Matching options MAST - Master Device ID0, 1, 2 - Device ID DFM - Programming mode, serial or default DF - Offset value for PAE and PAF Once a master reset has taken place, the device must be programmed either serially or via the default method before any read/write operations can begin. See Figure 4, Master Reset for relevant timing. PARTIAL RESET A Partial Reset is a means by which the user can reset both the read and write pointers of a single queue that has been setup within a multi-queue device. Before a partial reset can take place on a queue, the respective queue must be selected on both the read port and write port a minimum of 2 RCLK and 2 WCLK cycles before the PRS goes LOW. The partial reset is then performed by toggling the PRS input from HIGH to LOW to HIGH, maintaining the LOW state for at least one WCLK and one RCLK cycle. Once a partial reset has taken place a minimum of 3 WCLK and 3 RCLK cycles must occur before enabled writes or reads can occur. A Partial Reset only resets the read and write pointers of a given queue, a partial reset will not effect the overall configuration and setup of the multi-queue device and its queues. See Figure 5, Partial Reset for relevant timing. SERIAL PROGRAMMING The multi-queue flow-control device is a fully programmable device, providing the user with flexibility in how queues are configured in terms of the number of queues, depth of each queue and position of the PAF/PAE flags within respective queues. All user programming is done via the serial port after a master reset has taken place. Internally the multi-queue device has setup registers which must be serially loaded, these registers contain values for every queue within the device, such as the depth and PAE/PAF offset values. The IDT72V51546/72V51556 devices are capable of up to 32 queues and therefore contain 32 sets of registers for the setup of each queue. During a Master Reset if the DFM (Default Mode) input is LOW, then the device will require serial programming by the user. It is recommended that the user utilize a `C' program provided by IDT, this program will prompt the user for all information regarding the multi-queue setup. The program will then generate a serial bit stream which should be serially loaded into the device via the serial port. For the IDT72V51546/72V51556 devices the serial programming requires a total number of serially loaded bits per device, (SCLK cycles with SENI enabled), calculated by: 19+(Qx72) where Q is the number of queues the user wishes to setup within the device. Please refer to the separate Application Note, AN-303 for recommended control of the serial programming port. Once the master reset is complete and MRS is HIGH, the device can be serially loaded. Data present on the SI (serial in), input is loaded into the serial port on a rising edge of SCLK (serial clock), provided that SENI (serial in
17
enable), is LOW. Once serial programming of the device has been successfully completed the device will indicate this via the SENO (serial output enable) going active, LOW. Upon detection of completion of programming, the user should cease all programming and take SENI inactive, HIGH. Note, SENO follows SENI once programming of a device is complete. Therefore, SENO will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENO will also go HIGH. The operation of the SO output is similar, when programming of a given device is complete, the SO output will follow the SI input. If devices are being used in expansion mode the serial ports of devices should be cascaded. The user can load all devices via the serial input port control pins, SI & SENI, of the first device in the chain. Again, the user may utilize the `C' program to generate the serial bit stream, the program prompting the user for the number of devices to be programmed. The SENO and SO (serial out) of the first device should be connected to the SENI and SI inputs of the second device respectively and so on, with the SENO & SO outputs connecting to the SENI & SI inputs of all devices through the chain. All devices in the chain should be connected to a common SCLK. The serial output port of the final device should be monitored by the user. When SENO of the final device goes LOW, this indicates that serial programming of all devices has been successfully completed. Upon detection of completion of programming, the user should cease all programming and take SENI of the first device in the chain inactive, HIGH. As mentioned, the first device in the chain has its serial input port controlled by the user, this is the first device to have its internal registers serially loaded by the serial bit stream. When programming of this device is complete it will take its SENO output LOW and bypass the serial data loaded on the SI input to its SO output. The serial input of the second device in the chain is now loaded with the data from the SO of the first device, while the second device has its SENI input LOW. This process continues through the chain until all devices are programmed and the SENO of the final device goes LOW. Once all serial programming has been successfully completed, normal operations, (queue selections on the read and write ports) may begin. When connected in expansion mode, the IDT72V51546/72V51556 devices require a total number of serially loaded bits per device to complete serial programming, (SCLK cycles with SENI enabled), calculated by: n[19+(Qx72)] where Q is the number of queues the user wishes to setup within the device, where n is the number of devices in the chain. See Figure 6, Serial Port Connection and Figure 7, Serial Programming for connection and timing information. DEFAULT PROGRAMMING During a Master Reset if the DFM (Default Mode) input is HIGH the multiqueue device will be configured for default programming, (serial programming is not permitted). Default programming provides the user with a simpler, however limited means by which to setup the multi-queue flow-control device, rather than using the serial programming method. The default mode will configure a multi-queue device such that the maximum number of queues possible are setup, with all of the parts available memory blocks being allocated equally between the queues. The values of the PAE/PAF offsets is determined by the state of the DF (default) pin during a master reset. For the IDT72V51546/72V51556 devices the default mode will setup 32 queues, each queue being 1024 x36 and 2048 x36 deep respectively. For both devices the value of the PAE/PAF offsets is determined at master reset by the state of the DF input. If DF is LOW then both the PAE & PAF offset will be 8, if HIGH then the value is 128. When configuring the IDT72V51546/72V51556 devices in default mode the user simply has to apply WCLK cycles after a master reset, until SENO goes LOW, this signals that default programming is complete. These clock cycles are required for the device to load its internal setup registers. When a single multi-
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
queue device is used, the completion of device programming is signaled by the SENO output of a device going from HIGH to LOW. Note, that SENI must be held LOW when a device is setup for default programming mode. When multi-queue devices are connected in expansion mode, the SENI of the first device in a chain can be held LOW. The SENO of a device should connect to the SENI of the next device in the chain. The SENO of the final device is used to indicate that default programming of all devices is complete. When the final SENO goes LOW normal operations may begin. Again, all devices will be programmed with their maximum number of queues and the memory divided equally between them. Please refer to Figure 8, Default Programming. READING AND WRITING TO THE IDT MULTI-QUEUE FLOW CONTROL MANAGER The IDT72V51546/72V51556 multi-queue flow-control devices can be configured in two distinct modes, namely Standard Mode and Packet Mode. STANDARD MODE OPERATION (PKT = LOW on Master Reset) WRITE QUEUE SELECTION AND WRITE OPERATION (STANDARD MODE) The IDT72V51546/72V51556 multi-queue flow-control devices can be configured up to a maximum of 32 queues into which data can be written via a common write port using the data inputs (Din), write clock (WCLK) and write enable (WEN). The queue to be written is selected by the address present on the write address bus (WRADD) during a rising edge on WCLK while write address enable (WADEN) is HIGH. The state of WEN does not impact the
queue selection. The queue selection is requires 2 WCLK cycles. All subsequent data writes will be to this queue until another queue is selected. Standard mode operation is defined as individual words will be written to the device as opposed to Packet Mode where complete packets may be written. The write port is designed such that 100% bus utilization can be obtained. This means that data can be written into the device on every WCLK rising edge including the cycle that a new queue is being addressed. Changing queues requires a minimum of 2 WCLK cycles on the write port (see Figure 9, Write Queue Select, Write Operation and Full flag Operation). WADEN goes high signaling a change of queue (clock cycle "A"). The address on WRADD at that time determines the next queue. Data presented during that cycle ("A") and the next cycle ("B"), will be written to the active (old) queue, provided WEN is active LOW. If WEN is HIGH (inactive) for these two clock cycles, data will not be written in to the previous queue. The write port discrete full flag will update to show the full status of the newly selected queue (QX) at this last cycle's rising edge ("B"). Data present on the data input bus (Din), can be written into the newly selected queue (QX) on the rising edge of WCLK on the second cycle ("C") following a change of queue, provided WEN is LOW and the new queue is not full. If the newly selected queue is full at the point of its selection, any writes to that queue will be prevented. Data cannot be written into a full queue. Refer to Figure 9, Write Queue Select, Write Operation and Full flag Operation, Figure 10, Write Operations & First Word Fall Through for timing diagrams and Figure 11, Full Flag Timing in Expansion Mode for timing diagrams.
TABLE 1 -- WRITE ADDRESS BUS, WRADD[7:0]
Operation WCLK WADEN
Write Queue Select
FSTR
WRADD[7:0] 765 432 10
Device Select Write Queue Address (Compared to (5 bits = 32 Queues) ID0,1,2)
1
0
PAFn Quadrant Select
0
1
765
Device Select (Compared to ID0,1,2)
432
X X X
10
Quadrant Address
Quadrant Address 00 01 10 11
18
Queue Status on PAFn Bus Q0 : Q7 PAF0 : PAF7 Q8 : Q15 PAF0 : PAF7 Q16 : Q23 PAF0 : PAF7 Q24 : Q31 PAF0 : PAF7
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
READ QUEUE SELECTION AND READ OPERATION (STANDARD MODE) The IDT72V51546/72V51556 multi-queue flow-control devices can be configured up to a maximum of 32 queues which data can be read via a common read port using the data outputs (Qout), read clock (RCLK) and read enable (REN). An output enable, OE control pin is also provided to allow HighImpedance selection of the Qout data outputs. The multi-queue device read port operates in a mode similar to "First Word Fall Through" on a SuperSync IDT FIFO, but with the added feature of data output pipelining (see Figure 10, Write Operations & First Word Fall Through). The queue to be read is selected by the address presented on the read address bus (RDADD) during a rising edge on RCLK while read address enable (RADEN) is HIGH. The state of REN does not impact the queue selection. The queue selection is requires 2 RCLK cycles. All subsequent data reads will be from this queue until another queue is selected. Standard mode operation is defined as individual words will be read from the device as opposed to Packet Mode where complete packets may be read. The read port is designed such that 100% bus utilization can be obtained. This means that data can be read out of the device on every RCLK rising edge including the cycle that a new queue is being addressed. Changing queues requires a minimum of two RCLK cycles on the read port (see Figure 12, Read Queue Select, Read Operation). RADEN goes high signaling a change of queue (clock cycle "D"). The address on RDADD at that time determines the next queue. Data presented during that cycle ("D") will be read at "D" (+ tA), can be read from the active (old) queue (QP), provided REN is active LOW. If REN is HIGH (inactive) for this clock cycle, data will not be read from the previous queue. The next cycle's rising edge ("E"), the read port discrete empty flag will update to show the empty status of the newly selected
queue (QF). The internal pipeline is also loaded at this time ("D") with the last word from the previous (old) queue (QP) as well as the next word from the new queue (QF). Both of these words will fall through to the output register( provided the OE is asserted) consecutively (cycles "E" and "F" respectively) following the selection of the new queue regardless of the state of REN, unless the new queue (QF) is empty. If the newly selected queue is empty, any reads from that queue will be prevented. Data cannot be read from an empty queue. The last word in the data output register (from the previous queue), will remain on the data bus, but the output valid flag, OV will go HIGH, to indicate that the data present is no longer valid. This pipelining effect provides the user with 100% bus utilization, and brings about the possibility that a "NULL" queue may be required within a multi-queue device. Null queue operation is discussed in the next section. Remember that OE allows the user to place the data output bus (Qout) into High-Impedance and the data can be read in to the output register regardless of OE. Refer to Table 2, for Read Address Bus arrangement. Also, refer to Figures 12, 14, and 15 for read queue selection and read port operation timing diagrams. PACKET MODE OPERATION (PKT = HIGH on Master Reset) The Packet mode operation provides the capability where, user defined packets or frames can be written to the device as opposed to Standard mode where individual words are written. For clarification, in Packet Mode, a packet can be written to the device with the starting location designated as Transmit Start of Packet (TSOP) and the ending location designated as Transmit End of Packet (TEOP). In conjunction, a packet read from the device will be designated as Receive Start of Packet (RSOP) and a Receive End of Packet
TABLE 2 -- READ ADDRESS BUS, RDADD[7:0]
Operation RCLK
Read Queue Select
RADEN
ESTR
RDADD[7:0] 765 432 10
Device Select Read Queue Address (Compared to (5 bits = 32 Queues) ID0,1,2)
1
0
PAEn/PRn Quadrant Select
0
1
765
Device Select (Compared to ID0,1,2)
432
X X X
10
Quadrant Address
Quadrant Address 00 01 10 11
19
Queue Status on PAEn/PRn Bus Q0 : Q7 PAE0 : PAE7 Q8 : Q15 PAE0 : PAE7 Q16 : Q23 PAE0 : PAE7 Q24 : Q31 PAE0 : PAE7
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
(REOP). The minimum size for a packet is four words (SOP, two words of data and EOP). The almost empty flag bus becomes the "Packet Ready" PR flag bus when the device is configured for packet mode. Valid packets are indicated when both PR and OV are asserted. WRITE QUEUE SELECTION AND WRITE OPERATION (PACKET MODE) It is required that a full packet be written to a queue before moving to a different queue. The device requires two cycles to change queues. Packet mode, has 2 restrictions: <1> An extra word (or filler word) is required to be written after each packet on the cycle following the queue change to ensure the RSOP in the old queue is not read out on a queue change because of the first word fall through. <2> No SOP/EOP is allowed to read/written at cycle ("C" or "I") the next cycle after a queue change. For clock frequency (fs) of 133MHz and below see Application Note AN-398. In this mode, the write port may not obtain 100% bus utilization. Changing queues requires a minimum of two WCLK cycles on the write port (see Figure 16, Writing in Packet Mode during a Queue Change). WADEN goes high signaling a change of queue (clock cycle "B" or "H"). The address on WRADD at the rising edge of WCLK determines the next queue. Data presented on Din during that cycle ("B" or "H") can continue to be written to the active (old) queue (QA or QB respectively), provided WEN is LOW (active). If WEN is HIGH (inactive) for this clock cycle (H), data will not be written in to the previous queue (QB). The cycle following a request for queue change ("C" or "I") will require a filler word to be written to the device. This can be done by clocking the TEOP twice or by writing a filler word. In packet mode, the multiqueue is designed under the 2 restrictions listed previously. Note, an erroneous Packet Ready flag may occur if the EOP or SOP marker shows up at the next cycle after a queue change. To prevent an erroneous Packet Ready flag from occurring a filler word should be written into the old queue at the last clock cycle of writing. It is important to know that no SOP or EOP may be written into the device during this cycle ("C" or "I"). The write port discrete full flag will update to show the full status of the newly selected queue (QB) at this last cycle's rising edge ("C" or "I"). Data values presented on the data input bus (Din), can be written into the newly selected queue (QX) on the rising edge of WCLK on the second cycle ("D" or "J") following a request for change of queue, provided WEN is LOW (active) and the new queue is not full. If a selected queue is full (FF is LOW), then writes to that queue will be prevented. Note, data cannot be written into a full queue. Refer to Figure 16, Writing in Packet Mode during a Queue Change and Figure 18, Data Input (Transit) packet mode of Operation for timing diagrams. READ QUEUE SELECTION AND READ OPERATION (PACKET MODE) In packet Mode it is required that a full packet is read from a queue before moving to a different queue. The device requires two cycles to change queues. In Packet Mode, there are 2 restrictions <1> An extra word (or filler word) should have been inserted into the data stream after each packet to insure the RSOP in the old queue is not read out on a queue change because of the first word fall through and this word should be discarded. <2> No EOP/SOP is allowed to be read/written at cycle ("C" or "I") the next cycle after a queue change). For clock frequency of 133Mhz and below see Application Note AN398. In this mode, the read port may not obtain 100% bus utilization. Changing queues requires a minimum of two RCLK cycles on the read port (see Figure 17, Reading in Packet Mode during a Queue Change). RADEN goes high signaling a change of queue (clock cycle "B" or "I"). The address on RDADD at the rising edge of RCLK determines the queue. As illustrated in Figure 17 during cycle ("B"), data can be read from the active (old) queue (QA)), provided both REN and OE are LOW (active) simultaneously with changing queues. REOP for packet located in queue (QA) must be read before
a queue change request is made ("B"). If REN is HIGH (inactive) for this clock cycle ("I"), data will not be read from the previous queue (QB). In applications where the multi-queue flow-control device is connected to a shared bus, an output enable, OE control pin is also provided to allow High-Impedance selection of the data outputs (Qout). With reference to Figure 17 when changing queues, a packet marker (SOP or EOP) should not be read on cycle ("C" or "I"). Reading a SOP or EOP should not occur during the cycles required for a queue change. It is also recommended that a queue change should not occur once the reading of the packet has commenced. The EOP marker of the packet prior to a queue change should be read on or before the queue change. If the EOP word is read before a queue change, REN can be pulled high to disable further reads. When the queue change is initiated, the filler word written into the current queue after the EOP word will fall through followed by and the first word from the new queue. Refer to Figure 17, Reading in Packet Mode during a Queue Change as well as Figures 12, 14, and 15 for timing diagrams and Table 2, for Read Address bus arrangement. Note, the almost empty flag bus becomes the "Packet Ready" flag bus when the device is configured for packet mode. PACKET READY FLAG The multi-queue flow-control device provides the user with a Packet Ready feature. During a Master Reset the logic "1" (HIGH) on the PKT input signal (packet mode select), configures the device in packet mode. The PR discrete flag, provides a packet ready status of the active queue selected on the read port. A packet ready status is individually maintained on all queues; however only the queue selected on the read port has its packet ready status indicated on the PR output flag. A packet is available on the output for reading when both PR and OV are asserted LOW. If less than a full packet is available, the PR flag will be HIGH (packet not ready). In packet mode, no words can be read from a queue until a complete packet has been written into that queue, regardless of REN. When packet mode is selected the Programmable Almost Empty bus, PAEn, becomes the Packet Ready bus, PRn. When configured in Direct Bus (FM = LOW during a master reset), the PRn bus provides packet ready status in 8 queue increments. The PRn bus supports either Polled or Direct modes of operation. The PRn mode of operation is configured through the Flag Mode (FM) bit during a Master Reset. When the multi-queue is configured for packet mode operation, the device must also be configured for 36 bit write data bus and 36 bit read data bus. The two most significant bits of the 36-bit data bus are used as "packet markers". On the write port these are bits D34 (Transmit Start of Packet,) D35 (Transmit End of Packet) and on the read port Q34, Q35. All four bits are monitored by the packet control logic as data is written into and read out from the queues. The packet ready status for individual queues is then determined by the packet ready logic. On the write port D34 is used to "mark" the first word being written into the selected queue as the "Transmit Start of Packet", TSOP. To further clarify, when the user requires a word being written to be marked as the start of a packet, the TSOP input (D34) must be HIGH for the same WCLK rising edge as the word that is written. The TSOP marker is stored in the queue along with the data it was written in until the word is read out of the queue via the read port. On the write port D35 is used to "mark" the last word of the packet currently being written into the selected queue as the "Transmit End of Packet" TEOP. When the user requires a word being written to be marked as the end of a packet, the TEOP input must be HIGH for the same WCLK rising edge as the word that is written in. The TEOP marker is stored in the queue along with the data it was written in until the word is read out of the queue via the read port.
20
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TABLE 5 -- PACKET MODE VALID BYTE
D34/Q34
MOD 1 D33/Q33
MOD 2 D32/Q32
D35/Q35
D31/Q31
D23/Q23
D15/Q15
EOP
SOP
BYTE D
BYTE C
BYTE B
D7/Q7
BYTE A
TMOD1 (D33) RMOD1 (Q33) 0 0 1 1
TMOD2 (D32) RMOD2 (Q32) 0 1 0 1
VALID BYTES A, B, C, D A A, B A, B, C
5904 drw07
NOTE: Packet Mode is only available when the Input Port and Output Port are 36 bits wide.
The packet ready logic monitors all start and end of packet markers both as they enter respective queues via the write port and as they exit queues via the read port. The multi-queue internal logic increments and decrements a packet counter, which is provided for each queue. The functionality of the packet ready logic provides status as to whether at least one full packet of data is available within the selected queue. A partial packet in a queue is regarded as a packet not ready and PR (active LOW) will be HIGH. In Packet mode, no words can be read from a queue until at least one complete packet has been written into the queue, regardless of REN. For example, if a TSOP has been written and some number of words later a TEOP is written a full packet of data is deemed to be available, and the PR flag and OV will go active LOW. Consequently if reads begin from a queue that has only one complete packet and the RSOP is detected on the output port as data is being read out, PR will go inactive HIGH. OV will remain LOW indicating there is still valid data being read out of that queue until the REOP is read. The user may proceed with the reading operation until the current packet has been read out and no further complete packets are available. If during that time another complete packet has been written into the queue and the PR flag will again gone active, then reads from the new packet may follow after the current packet has been completely read out. The packet counters therefore look for start of packet markers followed by end of packet markers and regard data in between the TSOP and TEOP as a full packet of data. The packet monitoring has no limitation as to how many packets are written into a queue, the only constraint is the depth of the queue. Note, there is a minimum allowable packet size of four words, inclusive of the TSOP marker and TEOP marker. The packet logic does expect a TSOP marker to be followed by a TEOP marker. If a second TSOP marker is written after a first, it is ignored and the logic regards data between the first TSOP and the first subsequent TEOP as the full packet. The same is true for TEOP; a second consecutive TEOP mark is ignored. On the read side the user should regard a packet as being between the first RSOP and the first subsequent REOP and disregard consecutive RSOP markers and/or REOP markers. This is why a TEOP may be written twice, using the second TEOP as the filler word. As an example, the user may also wish to implement the use of an "Almost End of Packet"(AEOP) marker. For example, the AEOP can be assigned to data input bit D33. The purpose of this AEOP marker is to provide an indicator
21
that the end of packet is a fixed (known) number of reads away from the end of packet. This is a useful feature when due to latencies within the system, monitoring the REOP marker alone does not prevent "over reading" of the data from the queue selected. For example, an AEOP marker set 4 writes before the TEOP marker provides the device connected to the read port with and "almost end of packet" indication 4 cycles before the end of packet. The AEOP can be set any number of words before the end of packet determined by user requirements or latencies involved in the system. See Figure 17, Reading in Packet Mode during a Queue Change, Figure 18, Data Input (Transmit) Packet Mode of Operation and Figure 19, Data Output (Receive) Packet Mode of Operation. PACKET MODE - MODULO OPERATION The internal packet ready control logic performs no operation on these modulo bits, they are only informational bits that are passed through with the respective data byte(s). When utilizing the multi-queue flow-control device in packet mode, the user may also want to consider the implementation of "Modulo" operation or "valid byte marking". Modulo operation may be useful when the packets being transferred through a queue are in a specific byte arrangement even though the data bus width is 36 bits. In Modulo operation the user can concatenate bytes to form a specific data string through the multi-queue device. A possible scenario is where a limited number of bytes are extracted from the packet for either analysis or filtered for security protection. This will only occur when the first 36 bit word of a packet is written in and the last 36 bit word of packet is written in. The modulo operation is a means by which the user can mark and identify specific data within the Queue. On the write port data input bits, D32 (transmit modulo bit 2, TMOD2) and D33 (transmit modulo bit 1, TMOD1) can be used as data markers. An example of this could be to use D32 and D33 to code which bytes of a word are part of the packet that is also being marked as the "Start of Marker" or "End of Marker". Conversely on the read port when reading out these marked words, data outputs Q32 (receive modulo bit 2, RMOD2) and Q33 (receive modulo bit 1, RMOD1) will pass on the byte validity information for that word. Refer to Table 5 for one example of how the modulo bits may be setup and used. See Figure 18, Data Input (Transmit) Packet Mode of Operation and Figure 19, Data Output (Receive) Packet Mode of Operation.
D0/Q0
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
NULL QUEUE OPERATION (OF THE READ PORT) Pipelining of data to the output port enables the device to provide 100% bus utilization in standard mode. Data can be read out of the multi-queue flow-control device on every RCLK cycle regardless of queue switches or other operations. The device architecture is such that the pipeline is constantly filled with the next words in a selected queue to be read out, again providing 100% bus utilization. This type of architecture does assume that the user is constantly switching queues such that during a queue switch, the last data word required from the previous queue will fall through the pipeline to the output. Note, that if reads cease at the empty boundary of a queue, then the last word will automatically flow through the pipeline to the output. Null Q operation requires that a user only uses 31 queues in the 32 multiqueue flow-control device, the 32nd queue address (xxx 11111) of the device now is assigned as the null queue. (Note, any unused queue can be assigned as the Null queue). During device programming the user should simply program between 1 and 31 queues, the 32nd queue will automatically default to a null queue. (Note, that in expansion mode a user may want to assign a null queue in each device). Note, this option requires that the user must select serial programming and configure the device to be 31 queues, (or less). The default mode of device programming should not be selected, (default mode automatically sets up 32 queues, with the memory equally divided between queues). If Default mode is selected and the user wishes to assign one queue as the "Null-Q", extra care must be taken so as not to write data to the "NullQ", this is very important. A null queue can be selected when no further reads are required from a previously selected queue. Changing to a null queue will continue to propagate data in the pipeline to the previous queue's output. The Null Q can remain selected until a data becomes available in another queue for reading. The NullQ can be utilized in either standard or packet mode. Note: If the user switches the read port to the null queue, this queue is seen as and treated as an empty queue, therefore after switching to the null queue the last word from the previous queue will remain in the output register and the OV flag will go HIGH, indicating data is not valid. The Null queue operation only has significance to the read port of the multiqueue, it is a means to force data through the pipeline to the output. Null Q selection and operation has no meaning on the write port of the device. Also, refer to Figure 20, Read Operation and Null Queue Select for diagram. PAFn FLAG BUS OPERATION The IDT72V51546/72V51556 multi-queue flow-control devices can be configured for up to 32 queues, each queue having its own almost full status. An active queue has its flag status output to the discrete flags, FF and PAF, on the write port. Queues that are not selected for a write operation can have their PAF status monitored via the PAFn bus. The PAFn flag bus is 8 bits wide, so that 8 queues at a time can have their status output to the bus. If 9 or more queues are setup within a device then there are 2 methods by which the device can share the bus between queues, "Direct" mode and "Polled" mode depending on the state of the FM (Flag Mode) input during a Master Reset. If 8 or less queues are setup within a device then each will have its own dedicated output from the bus. If 8 or less queues are setup in single device mode, it is recommended to configure the PAFn bus to polled mode as it does not require using the write address (WRADD). EXPANDING UP TO 256 QUEUES OR PROVIDING DEEPER QUEUES Expansion can take place using either the standard mode or the packet mode. In the 32 queue multi-queue device, the WRADD address bus is 8 bits wide. The 5 Least Significant bits (LSbs) are used to address one of the 32 available queues within a single multi-queue device. The 3 Most Significant bits
(MSbs) are used when a device is connected in expansion mode with up to 8 devices connected in width expansion, each device having its own 3-bit address. When logically expanded with multiple parts, each device is statically setup with a unique chip ID code on the ID pins, ID0, ID1, and ID2. A device is selected when the 3 Most Significant bits of the WRADD address bus matches a 3-bit ID code. The maximum logical expansion is 256 queues (32 queues x 8 devices) or a minimum of 8 queues (1 queue per device x 8 devices), each of the maximum size of the individual memory device. Note: The WRADD bus is also used in conjunction with FSTR (almost full flag bus strobe), to address the almost full flag bus during direct mode of operation. Refer to Table 1, for Write Address bus arrangement. Also, refer to Figure 11, Full Flag Timing Expansion Mode, Figure 13, Output Valid Flag Timing (In Expansion Mode), and Figure 32, Multi-Queue Expansion Diagram, for timing diagrams. BUS MATCHING OPERATION Bus Matching operation between the input port and output port is available. During a master reset of the multi-queue the state of the three setup pins, BM (Bus Matching), IW (Input Width) and OW (Output Width) determine the input and output port bus widths as per the selections shown in Table 3, "Bus Matching Set-Up". 9 bit bytes, 18 bit words and 36 bit long words can be written into and read from the queues provided that at least one of the ports is setup for x36 operation. When writing to or reading from the multi-queue in a bus matching mode, the device orders data in a "Little Endian" format. See Figure 3, Bus Matching Byte Arrangement for details. The Full flag and Almost Full flag operation is always based on writes and reads of data widths determined by the write port width. For example, if the input port is x36 and the output port is x9, then four data reads from a full queue will be required to cause the full flag to go HIGH (queue not full). Conversely, the Output Valid flag and Almost Empty flag operations are always based on writes and reads of data widths determined by the read port. For example, if the input
TABLE 3 BUS-MATCHING SET-UP
x36 DEVICE BM 0 1 1 1 1 IW X 0 0 1 1 OW X 0 1 0 1 Write Port x36 x36 x36 x18 x9 Read Port x36 x18 x9 x36 x36
port is x18 and the output port is x36, two write operations will be required to cause the output valid flag of an empty queue to go LOW, output valid (queue is not empty). Note, that the input port serves all queues within a device, as does the output port, therefore the input bus width to all queues is equal (determined by the input port size) and the output bus width from all queues is equal (determined by the output port size). FULL FLAG OPERATION The multi-queue flow-control device provides a single Full Flag output, FF. The FF flag output provides a full status of the queue currently selected on the write port for write operations. Internally the multi-queue flow-control device monitors and maintains a status of the full condition of all queues within it, however
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
only the queue that is selected for write operations has its full status output to the FF flag. This dedicated flag is often referred to as the "active queue full flag". When queue switches are being made on the write port, the FF flag output will switch to the new queue and provide the user with the new queue status, on the cycle after a new queue selection is made. The user then has a full status for the new queue one cycle ahead of the WCLK rising edge that data can be written into the new queue. That is, a new queue can be selected on the write port via the WRADD bus, WADEN enable and a rising edge of WCLK. On the next rising edge of WCLK, the FF flag output will show the full status of the newly selected queue. On the second rising edge of WCLK following the queue selection, data can be written into the newly selected queue provided that data and enable setup & hold times are met. Note, the FF flag will provide status of a newly selected queue one WCLK cycle after queue selection, which is one cycle before data can be written to that queue. This prevents the user from writing data to a queue that is full, (assuming that a queue switch has been made to a queue that is actually full). The FF flag is synchronous to the WCLK and all transitions of the FF flag occur based on a rising edge of WCLK. Internally the multi-queue device monitors and keeps a record of the full status for all queues. It is possible that the status of a FF flag maybe changing internally even though that flag is not the active queue flag (selected on the write port). A queue selected on the read port may experience a change of its internal full flag status based on read operations. See Figure 9, Write Queue Select, Write Operation and Full Flag Operation and Figure 11, Full Flag Timing in Expansion Mode for timing information. EXPANSION MODE - FULL FLAG OPERATION When multi-queue devices are connected in Expansion mode the FF flags of all devices should be connected together, such that a system controller monitoring and managing the multi-queue devices write port only looks at a single FF flag (as opposed to a discrete FF flag for each device). This FF flag is only pertinent to the queue being selected for write operations at that time. Remember, that when in expansion mode only one multi-queue device can be written to at any moment in time, thus the FF flag provides status of the active queue on the write port. This connection of flag outputs to create a single flag requires that the FF flag output have a High-Impedance capability, such that when a queue selection is made only a single device drives the FF flag bus and all other FF flag outputs connected to the FF flag bus are placed into High-Impedance. The user does not have to select this High-Impedance state, a given multi-queue flow-control device will automatically place its FF flag output into High-Impedance when none of its queues are selected for write operations. When queues within a single device are selected for write operations, the FF flag output of that device will maintain control of the FF flag bus. Its FF flag will simply update between queue switches to show the respective queue full status. The multi-queue device places its FF flag output into High-Impedance based on the 3 bit ID code found in the 3 most significant bits of the write queue address bus, WRADD. If the 3 most significant bits of WRADD match the 3 bit ID code setup on the static inputs, ID0, ID1 and ID2 then the FF flag output of the respective device will be in a Low-Impedance state. If they do not match, then the FF flag output of the respective device will be in a High-Impedance state. See Figure 11, Full Flag Timing in Expansion Mode for details of flag operation, including when more than one device is connected in expansion. OUTPUT VALID FLAG OPERATION The multi-queue flow-control device provides a single Output Valid flag output, OV. The OV provides an empty status or data output valid status for the data word currently available on the output register of the read port. The rising
edge of an RCLK cycle that places new data onto the output register of the read port, also updates the OV flag to show whether or not that new data word is actually valid. Internally the multi-queue flow-control device monitors and maintains a status of the empty condition of all queues within it, however only the queue that is selected for read operations has its output valid (empty) status output to the OV flag, giving a valid status for the word being read at that time. The nature of the first word fall through operation means that when the last data word is read from a selected queue, the OV flag will go HIGH on the next enabled read, that is, on the next rising edge of RCLK while REN is LOW. When queue switches are being made on the read port, the OV flag will switch to show status of the new queue in line with the data output from the new queue. When a queue selection is made the first data from that queue will appear on the Qout data outputs 2 RCLK cycles later, the OV will change state to indicate validity of the data from the newly selected queue on this 2nd RCLK cycle also. The previous cycles will continue to output data from the previous queue and the OV flag will indicate the status of those outputs. Again, the OV flag always indicates status for the data currently present on the output register. The OV flag is synchronous to the RCLK and all transitions of the OV flag occur based on a rising edge of RCLK. Internally the multi-queue device monitors and keeps a record of the output valid (empty) status for all queues. It is possible that the status of an OV flag may be changing internally even though that respective flag is not the active queue flag (selected on the read port). A queue selected on the write port may experience a change of its internal OV flag status based on write operations, that is, data may be written into that queue causing it to become "not empty". See Figure 12, Read Queue Select, Read Operation and Figure 13, Output Valid Flag Timing for details of the timing. EXPANSION MODE - OUTPUT VALID FLAG OPERATION When multi-queue devices are connected in Expansion mode, the OV flags of all devices should be connected together, such that a system controller monitoring and managing the multi-queue devices read port only looks at a single OV flag (as opposed to a discrete OV flag for each device). This OV flag is only pertinent to the queue being selected for read operations at that time. Remember, that when in expansion mode only one multi-queue device can be read from at any moment in time, thus the OV flag provides status of the active queue on the read port. This connection of flag outputs to create a single flag requires that the OV flag output have a High-Impedance capability, such that when a queue selection is made only a single device drives the OV flag bus and all other OV flag outputs connected to the OV flag bus are placed into High-Impedance. The user does not have to select this High-Impedance state, a given multi-queue flow-control device will automatically place its OV flag output into High-Impedance when none of its queues are selected for read operations. When queues within a single device are selected for read operations, the OV flag output of that device will maintain control of the OV flag bus. Its OV flag will simply update between queue switches to show the respective queue output valid status. The multi-queue device places its OV flag output into High-Impedance based on the 3 bit ID code found in the 3 most significant bits of the read queue address bus, RDADD. If the 3 most significant bits of RDADD match the 3 bit ID code setup on the static inputs, ID0, ID1 and ID2 then the OV flag output of the respective device will be in a Low-Impedance state. If they do not match, then the OV flag output of the respective device will be in a High-Impedance state. See Figure 13, Output Valid Flag Timing for details of flag operation, including when more than one device is connected in expansion.
23
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ALMOST FULL FLAG As previously mentioned the multi-queue flow-control device provides a single Programmable Almost Full flag output, PAF. The PAF flag output provides a status of the almost full condition for the active queue currently selected on the write port for write operations. Internally the multi-queue flow-control device monitors and maintains a status of the almost full condition of all queues within it, however only the queue that is selected for write operations has its full status output to the PAF flag. This dedicated flag is often referred to as the "active queue almost full flag". The position of the PAF flag boundary within a queue can be at any point within that queues depth. This location can be user programmed via the serial port or one of the default values (8 or 128) can be selected if the user has performed default programming. As mentioned, every queue within a multi-queue device has its own almost full status, when a queue is selected on the write port, this status is output via the PAF flag. The PAF flag value for each queue is programmed during multi-queue device programming (along with the number of queues, queue depths and almost empty values). The PAF offset value, m, for a respective queue can be programmed to be anywhere between `0' and `D', where `D' is the total memory depth for that queue. The PAF value of different queues within the same device can be different values. When queue switches are being made on the write port, the PAF flag output will switch to the new queue and provide the user with the new queue status, on the second cycle after a new queue selection is made, on the same WCLK cycle that data can actually be written to the new queue. That is, a new queue can be selected on the write port via the WRADD bus, WADEN enable and a rising edge of WCLK. On the second rising edge of WCLK following a queue selection, the PAF flag output will show the full status of the newly selected queue. The PAF is flag output is double register buffered, so when a write operation occurs at the almost full boundary causing the selected queue status to go almost full the PAF will go LOW 2 WCLK cycles after the write. The same is true when a read occurs, there will be a 2 WCLK cycle delay after the read operation. So the PAF flag delays are: from a write operation to PAF flag LOW is 2 WCLK + tWAF The delay from a read operation to PAF flag HIGH is tSKEW2 + WCLK + tWAF Note, if tSKEW is violated there will be one added WCLK cycle delay. The PAF flag is synchronous to the WCLK and all transitions of the PAF flag occur based on a rising edge of WCLK. Internally the multi-queue device monitors and keeps a record of the almost full status for all queues. It is possible that the status of a PAF flag maybe changing internally even though that flag is not the active queue flag (selected on the write port). A queue selected on the read port may experience a change of its internal almost full flag status based on read operations. The multi-queue flow-control device also provides a duplicate of the PAF flag on the PAF[7:0] flag bus, this will be discussed in detail in a later section of the data sheet. See Figures 22 and 23 for Almost Full flag timing and queue switching.
ALMOST EMPTY FLAG As previously mentioned the multi-queue flow-control device provides a single Programmable Almost Empty flag output, PAE. The PAE flag output provides a status of the almost empty condition for the active queue currently selected on the read port for read operations. Internally the multi-queue flowcontrol device monitors and maintains a status of the almost empty condition of all queues within it, however only the queue that is selected for read operations has its empty status output to the PAE flag. This dedicated flag is often referred to as the "active queue almost empty flag". The position of the PAE flag boundary within a queue can be at any point within that queues depth. This location can be user programmed via the serial port or one of the default values (8 or 128) can be selected if the user has performed default programming. As mentioned, every queue within a multi-queue device has its own almost empty status, when a queue is selected on the read port, this status is output via the PAE flag. The PAE flag value for each queue is programmed during multiqueue device programming (along with the number of queues, queue depths and almost full values). The PAE offset value, n, for a respective queue can be programmed to be anywhere between `0' and `D', where `D' is the total memory depth for that queue. The PAE value of different queues within the same device can be different values. When queue switches are being made on the read port, the PAE flag output will switch to the new queue and provide the user with the new queue status, on the second cycle after a new queue selection is made, on the same RCLK cycle that data actually falls through to the output register from the new queue. That is, a new queue can be selected on the read port via the RDADD bus, RADEN enable and a rising edge of RCLK. On the second rising edge of RCLK following a queue selection, the data word from the new queue will be available at the output register and the PAE flag output will show the empty status of the newly selected queue. The PAE is flag output is double register buffered, so when a read operation occurs at the almost empty boundary causing the selected queue status to go almost empty the PAE will go LOW 2 RCLK cycles after the read. The same is true when a write occurs, there will be a 2 RCLK cycle delay after the write operation. So the PAE flag delays are: from a read operation to PAE flag LOW is 2 RCLK + tRAE The delay from a write operation to PAE flag HIGH is tSKEW2 + RCLK + tRAE Note, if tSKEW is violated there will be one added RCLK cycle delay. The PAE flag is synchronous to the RCLK and all transitions of the PAE flag occur based on a rising edge of RCLK. Internally the multi-queue device monitors and keeps a record of the almost empty status for all queues. It is possible that the status of a PAE flag maybe changing internally even though that flag is not the active queue flag (selected on the read port). A queue selected on the write port may experience a change of its internal almost empty flag status based on write operations. The multi-queue flow-control device also provides a duplicate of the PAE flag on the PAE[7:0] flag bus, this will be discussed in detail in a later section of the data sheet. See Figures 24 and 25 for Almost Empty flag timing and queue switching.
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TABLE 4 -- FLAG OPERATION BOUNDARIES & TIMING
I/O Set-Up Output Valid, OV Flag Boundary OV Boundary Condition OV Goes LOW after 1st Write (see note 1 below for timing) OV Goes LOW after 1st Write (see note 2 below for timing) OV Goes LOW after 1st Write (see note 1 below for timing) OV Goes LOW after 1st Write (see note 1 below for timing) OV Goes LOW after 1st Write (see note 1 below for timing) OV Goes LOW after 1st Write (see note 1 below for timing) I/O Set-Up Full Flag, FF Boundary FF Boundary Condition FF Goes LOW after D+1 Writes (see note below for timing) FF Goes LOW after D Writes (see note below for timing) FF Goes LOW after D Writes (see note below for timing) FF Goes LOW after D Writes (see note below for timing) FF Goes LOW after D Writes (see note below for timing) FF Goes LOW after D Writes (see note below for timing) FF Goes LOW after ([D+1] x 2) Writes (see note below for timing) FF Goes LOW after (D x 2) Writes (see note below for timing) FF Goes LOW after ([D+1] x 4) Writes (see note below for timing) FF Goes LOW after (D x 4) Writes (see note below for timing) In36 to out36 (Almost Empty Mode) (Both ports selected for same queue when the 1st Word is written in) In36 to out36 (Packet mode) (Both ports selected for same queue when the 1st Word is written in) In36 to out18 (Both ports selected for same queue when the 1st Word is written in) In36 to out9 (Both ports selected for same queue when the 1st Word is written in) In18 to out36 (Both ports selected for same queue when the 1st Word is written in) In9 to out36 (Both ports selected for same queue when the 1st Word is written in)
In36 to out36 (Both ports selected for same queue when the 1st Word is written in) In36 to out36 (Write port only selected for queue when the 1st Word is written in) In36 to out18 (Both ports selected for same queue when the 1st Word is written in) In36 to out18 (Write port only selected for queue when the 1st Word is written in) In36 to out9 (Both ports selected for same queue when the 1st Word is written in) In36 to out9 (Write port only selected for queue when the 1st Word is written in) In18 to out36 (Both ports selected for same queue when the 1st Word is written in) In18 to out36 (Write port only selected for queue when the 1st Word is written in) In9 to out36 (Both ports selected for same queue when the 1st Word is written in) In9 to out36 (Write port only selected for queue when the 1st Word is written in)
NOTE: 1. OV Timing Assertion: Write to OV LOW: tSKEW1 + RCLK + tROV If tSKEW1 is violated there may be 1 added clock: tSKEW1 + 2 RCLK + tROV De-assertion: Read Operation to OV HIGH: tROV 2. OV Timing when in Packet mode (36 in to 36 out only) Assertion: Write to OV LOW: tSKEW4 + RCLK + tROV If tSKEW4 is violated there may be 1 added clock: tSKEW4 + 2 RCLK + tROV De-assertion: Read Operation to OV HIGH: tROV
NOTE: D = Queue Depth FF Timing Assertion: Write Operation to FF LOW: tWFF De-assertion: Read to FF HIGH: tSKEW1 + tWFF If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF
Programmable Almost Full Flag, PAF & PAFn Bus Boundary I/O Set-Up PAF & PAFn Boundary in36 to out36 PAF/PAFn Goes LOW after (Both ports selected for same queue when the 1st D+1-m Writes Word is written in until the boundary is reached) (see note below for timing) in36 to out36 PAF/PAFn Goes LOW after (Write port only selected for same queue when the D-m Writes 1st Word is written in until the boundary is reached) (see note below for timing) in36 to out18 PAF/PAFn Goes LOW after D-m Writes (see below for timing) in36 to out9 PAF/PAFn Goes LOW after D-m Writes (see below for timing) in18 to out36 PAF/PAFn Goes LOW after ([D+1-m] x 2) Writes (see note below for timing) in9 to out36 PAF/PAFn Goes LOW after ([D+1-m] x 4) Writes (see note below for timing) 25
NOTE: D = Queue Depth m = Almost Full Offset value. Default values: if DF is LOW at Master Reset then m = 8 if DF is HIGH at Master Reset then m= 128 PAF Timing Assertion: Write Operation to PAF LOW: 2 WCLK + tWAF De-assertion: Read to PAF HIGH: tSKEW2 + WCLK + tWAF If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF PAFn Timing Assertion: Write Operation to PAFn LOW: 2 WCLK* + tPAF De-assertion: Read to PAFn HIGH: tSKEW3 + WCLK* + tPAF If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF * If a queue switch is occurring on the write port at the point of flag assertion or de-assertion there may be one additional WCLK clock cycle delay.
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TABLE 4 -- FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
Programmable Almost Empty Flag, PAE Boundary I/O Set-Up in36 to out36 (Both ports selected for same queue when the 1st Word is written in until the boundary is reached) in36 to out18 (Both ports selected for same queue when the 1st Word is written in until the boundary is reached) in36 to out9 (Both ports selected for same queue when the 1st Word is written in until the boundary is reached) in18 to out36 (Both ports selected for same queue when the 1st Word is written in until the boundary is reached) in9 to out36 (Both ports selected for same queue when the 1st Word is written in until the boundary is reached) PAE Assertion PAE Goes HIGH after n+2 Writes (see note below for timing) PAE Goes HIGH after n+1 Writes (see note below for timing) PAE Goes HIGH after n+1 Writes (see note below for timing) PAE Goes HIGH after ([n+2] x 2) Writes (see note below for timing) PAE Goes HIGH after ([n+2] x 4) Writes (see note below for timing) Programmable Almost Empty Flag Bus, PAEn Boundary I/O Set-Up in36 to out36 (Both ports selected for same queue when the 1st Word is written in until the boundary is reached) in36 to out36 (Write port only selected for same queue when the 1st Word is written in until the boundary is reached) in36 to out18 in36 to out9 in18 to out36 (Both ports selected for same queue when the 1st Word is written in until the boundary is reached) in18 to out36 (Write port only selected for same queue when the 1st Word is written in until the boundary is reached) in9 to out36 (Both ports selected for same queue when the 1st Word is written in until the boundary is reached) in9 to out36 (Write port only selected for same queue when the 1st Word is written in until the boundary is reached) PAEn Boundary Condition PAEn Goes HIGH after n+2 Writes (see note below for timing) PAEn Goes HIGH after n+1 Writes (see note below for timing) PAEn Goes HIGH after n+1 Writes (see below for timing) PAEn Goes HIGH after n+1 Writes (see below for timing) PAEn Goes HIGH after ([n+2] x 2) Writes (see note below for timing) PAEn Goes HIGH after ([n+1] x 2) Writes (see note below for timing) PAEn Goes HIGH after ([n+2] x 4) Writes (see note below for timing) PAEn Goes HIGH after ([n+1] x 4) Writes (see note below for timing)
NOTE: n = Almost Empty Offset value. Default values: if DF is LOW at Master Reset then n = 8 if DF is HIGH at Master Reset then n = 128 PAE Timing Assertion: Read Operation to PAE LOW: 2 RCLK + tRAE De-assertion: Write to PAE HIGH: tSKEW2 + RCLK + tRAE If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE
NOTE: n = Almost Empty Offset value. Default values: if DF is LOW at Master Reset then n = 8 if DF is HIGH at Master Reset then n = 128 PAEn Timing Assertion: Read Operation to PAEn LOW: 2 RCLK* + tPAE De-assertion: Write to PAEn HIGH: tSKEW3 + RCLK* + tPAE If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE * If a queue switch is occurring on the read port at the point of flag assertion or de-assertion there may be one additional RCLK clock cycle delay.
PACKET READY FLAG, PR BOUNDARY Assertion: Both the rising and falling edges of PR are synchronous to RCLK. PR Falling Edge occurs upon writing the first TEOP marker, on input D35, (assuming a TSOP marker, on input D34 has previously been written). i.e. a complete packet is available within a queue. Timing: From WCLK rising edge writing the TEOP word PR goes LOW after: tSKEW4 + 2 RCLK + tPR If tSKEW4 is violated: PR goes LOW after tSKEW4 + 3 RCLK + tPR (Please refer to Figure 18, Data Input (Transmit) Packet Mode of Operation, for timing diagram). De-assertion: PR Rising Edge occurs upon reading the last RSOP marker, from output Q34. i.e. there are no more complete packets available within the queue. Timing: From RCLK rising edge Reading the RSOP word the PR goes HIGH after: 2 RCLK + tPR (Please refer to Figure 19, Data Output (Receive) Packet Mode of Operation for timing diagram).
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PACKET READY FLAG BUS, PRn BOUNDARY Assertion: Both the rising and falling edges of PRn are synchronous to RCLK. PRn Falling Edge occurs upon writing the first TEOP marker, on input D35, (assuming a TSOP marker, on input D34 has previously been written). i.e. a complete packet is available within a queue. Timing: From WCLK rising edge writing the TEOP word PR goes LOW after: tSKEW4 + 2 RCLK* + tPAE If tSKEW4 is violated PRn goes LOW after tSKEW4 + 3 RCLK* + tPAE *If a queue switch is occurring on the read port at the point of flag assertion or de-assertion there may be one additional RCLK clock cycle delay. De-assertion: PR Rising Edge occurs upon reading the last RSOP marker, from output Q34. i.e. there are no more complete packets available within the queue. Timing: From RCLK rising edge Reading the RSOP word the PR goes HIGH after: 2 RCLK* + tPAE *If a queue switch is occurring on the read port at the point of flag assertion or de-assertion there may be one additional RCLK clock cycle delay.
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PAFn - DIRECT BUS If FM is LOW at master reset then the PAFn bus operates in Direct (addressed) mode. In direct mode the user can address the quadrant of queues they require to be placed on to the PAFn bus. For example, consider the operation of the PAFn bus when 26 queues have been setup. To output status of the first quadrant, Queue[0:7] the WRADD bus is used in conjunction with the FSTR (PAF flag strobe) input and WCLK. The address present on the 2 least significant bits of the WRADD bus with FSTR HIGH will be selected as the quadrant address on a rising edge of WCLK. So to address quadrant 1, Queue[0:7] the WRADD bus should be loaded with "xxxxxx00", the PAFn bus will change status to show the new quadrant selected 1 WCLK cycle after quadrant selection. PAFn[0:7] gets status of queues, Queue[0:7] respectively. To address the second quadrant, Queue[8:15], the WRADD address is "xxxxxx01". PAFn[0:7] gets status of queues, Queue[8:15] respectively. To address the third quadrant, Queue[16:23], the WRADD address is "xxxxxx10". PAF[0:7] gets status of queues, Queue[16:23] respectively. To address the fourth quadrant, Queue[24:31], the WRADD address is "xxxxxx11". PAF[0:1] gets status of queues, Queue[24:25] respectively. Remember, only 26 queues were setup, so when quadrant 4 is selected the unused outputs PAF[2:7] will be don't care states. Note, that if a read or write operation is occurring to a specific queue, say queue `x' on the same cycle as a quadrant switch which will include the queue `x', then there may be an extra WCLK cycle delay before that queues status is correctly shown on the respective output of the PAFn bus. However, the active PAF flag will show correct status at all times. Quadrants can be selected on consecutive clock cycles, that is the quadrant on the PAFn bus can change every WCLK cycle. Also, data present on the input bus, Din, can be written into a queue on the same WCLK rising edge that a quadrant is being selected, the only restriction being that a write queue selection and PAFn quadrant selection cannot be made on the same cycle. If 8 or less queues are setup then queues, Queue[0:7] have their PAF status output on PAF[0:7] constantly. When the multi-queue devices are connected in expansion of more than one device the PAFn busses of all devices are connected together, when switching between quadrants of different devices the user must utilize the 3 most significant bits of the WRADD address bus (as well as the 2 LSB's). These 3 MSB's correspond to the device ID inputs, which are the static inputs, ID0, ID1 & ID2. Please refer to Figure 27, PAFn - Direct Mode Quadrant Selection for timing information. Also refer to Table 1, Write Address Bus, WRADD. PAFn - POLLED BUS If FM is HIGH at master reset then the PAFn bus operates in Polled (looped) mode. In polled mode the PAFn bus automatically cycles through the 4 quadrants within the device regardless of how many queues have been setup in the part. Every rising edge of the WCLK causes the next quadrant to be loaded on the PAFn bus. The device configured as the master (MAST input tied HIGH), will take control of the PAFn after MRS goes LOW. For the whole WCLK cycle that the first quadrant is on PAFn the FSYNC (PAFn bus sync) output will be HIGH, for all other quadrants, this FSYNC output will be LOW. This FSYNC output provides the user with a mark with which they can synchronize to the PAFn bus, FSYNC is always HIGH for the WCLK cycle that the first quadrant of a device is present on the PAFn bus. When devices are connected in expansion mode, only one device will be set as the Master, MAST input tied HIGH, all other devices will have MAST tied LOW. The master device is the first device to take control of the PAFn bus and will place its first quadrant on the bus on the rising edge of WCLK after the MRS input goes HIGH. For the next 3 WCLK cycles the master device will maintain control of the PAFn bus and cycle its quadrants through it, all other
27
devices hold their PAFn outputs in High-Impedance. When the master device has cycled all of its quadrants it passes a token to the next device in the chain and that device assumes control of the PAFn bus and then cycles its quadrants and so on, the PAFn bus control token being passed on from device to device. This token passing is done via the FXO outputs and FXI inputs of the devices ("PAF Expansion Out" and "PAF Expansion In"). The FXO output of the master device connects to the FXI of the second device in the chain and the FXO of the second connects to the FXI of the third and so on. The final device in a chain has its FXO connected to the FXI of the first device, so that once the PAFn bus has cycled through all quadrants of all devices, control of the PAFn will pass to the master device again and so on. The FSYNC of each respective device will operate independently and simply indicate when that respective device has taken control of the bus and is placing its first quadrant on to the PAFn bus. When operating in single device mode the FXI input must be connected to the FXO output of the same device. In single device mode a token is still required to be passed into the device for accessing the PAFn bus. Please refer to Figure 30, PAFn Bus - Polled Mode for timing information. PAEn/PRn FLAG BUS OPERATION The IDT72V51546/72V51556 multi-queue flow-control devices can be configured for up to 32 queues, each queue having its own almost empty/ packet ready status. An active queue has its flag status output to the discrete flags, OV, PAE and PR, on the read port. Queues that are not selected for a read operation can have their PAE/PR status monitored via the PAEn/PRn bus. The PAEn/PRn flag bus is 8 bits wide, so that 8 queues at a time can have their status output to the bus. If 9 or more queues are setup within a device then there are 2 methods by which the device can share the bus between queues, "Direct" mode and "Polled" mode depending on the state of the FM (Flag Mode) input during a Master Reset. If 8 or less queues are setup within a device then each will have its own dedicated output from the bus. If 8 or less queues are setup in single device mode, it is recommended to configure the PAFn bus to polled mode as it does not require using the write address (WRADD). PAEn/PRn - DIRECT BUS If FM is LOW at master reset then the PAEn/PRn bus operates in Direct (addressed) mode. In direct mode the user can address the quadrant of queues they require to be placed on to the PAEn/PRn bus. For example, consider the operation of the PAEn/PRn bus when 26 queues have been setup. To output status of the first quadrant, Queue[0:7] the RDADD bus is used in conjunction with the ESTR (PAE/PR flag strobe) input and RCLK. The address present on the 2 least significant bits of the RDADD bus with ESTR HIGH will be selected as the quadrant address on a rising edge of RCLK. So to address quadrant 1, Queue[0:7] the RDADD bus should be loaded with "xxxxxx00", the PAEn/PRn bus will change status to show the new quadrant selected 1 RCLK cycle after quadrant selection. PAEn[0:7] gets status of queues, Queue[0:7] respectively. To address the second quadrant, Queue[8:15], the RDADD address is "xxxxxx01". PAEn[0:7] gets status of queues, Queue[8:15] respectively. To address the third quadrant, Queue[16:23], the RDADD address is "xxxxxx10". PAE[0:7] gets status of queues, Queue[16:23] respectively. To address the fourth quadrant, Queue[24:31], the RDADD address is "xxxxxx11". PAE[0:1] gets status of queues, Queue[24:25] respectively. Remember, only 26 queues were setup, so when quadrant 4 is selected the unused outputs PAE[2:7] will be don't care states. Note, that if a read or write operation is occurring to a specific queue, say queue `x' on the same cycle as a quadrant switch which will include the queue `x', then there may be an extra RCLK cycle delay before that queues status is correctly shown on the respective output of the PAEn/PRn bus.
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Quadrants can be selected on consecutive clock cycles, that is the quadrant on the PAEn/PRn bus can change every RCLK cycle. Also, data can be read out of a queue on the same RCLK rising edge that a quadrant is being selected, the only restriction being that a read queue selection and PAEn/PRn quadrant selection cannot be made on the same RCLK cycle. If 8 or less queues are setup then queues, Queue[0:7] have their PAE/PR status output on PAE[0:7] constantly. When the multi-queue devices are connected in expansion of more than one device the PAEn/PRn busses of all devices are connected together, when switching between quadrants of different devices the user must utilize the 3 most significant bits of the RDADD address bus (as well as the 2 LSB's). These 3 MSB's correspond to the device ID inputs, which are the static inputs, ID0, ID1 & ID2. Please refer to Figure 26, PAEn/PRn - Direct Mode Quadrant Selection for timing information. Also refer to Table 2, Read Address Bus, RDADD. PAEn - POLLED BUS If FM is HIGH at master reset then the PAEn/PRn bus operates in Polled (looped) mode. In polled mode the PAEn/PRn bus automatically cycles through the 4 quadrants within the device regardless of how many queues have been setup in the part. Every rising edge of the RCLK causes the next quadrant to be loaded on the PAEn/PRn bus. The device configured as the master (MAST input tied HIGH), will take control of the PAEn/PRn after MRS goes LOW. For the whole RCLK cycle that the first quadrant is on PAEn/PRn the ESYNC (PAEn/PRn bus sync) output will be HIGH, for all other quadrants, this ESYNC output will be LOW. This ESYNC output provides the user with a mark with which they can synchronize to the PAEn/PRn bus, ESYNC is
always HIGH for the RCLK cycle that the first quadrant of a device is present on the PAEn/PRn bus. When devices are connected in expansion mode, only one device will be set as the Master, MAST input tied HIGH, all other devices will have MAST tied LOW. The master device is the first device to take control of the PAEn/PRn bus and will place its first quadrant on the bus on the rising edge of RCLK after the MRS input goes LOW. For the next 3 RCLK cycles the master device will maintain control of the PAEn/PRn bus and cycle its quadrants through it, all other devices hold their PAEn/PRn outputs in High-Impedance. When the master device has cycled all of its quadrants it passes a token to the next device in the chain and that device assumes control of the PAEn/PRn bus and then cycles its quadrants and so on, the PAEn/PRn bus control token being passed on from device to device. This token passing is done via the EXO outputs and EXI inputs of the devices ("PAE Expansion Out" and "PAE Expansion In"). The EXO output of the master device connects to the EXI of the second device in the chain and the EXO of the second connects to the EXI of the third and so on. The final device in a chain has its EXO connected to the EXI of the first device, so that once the PAEn/PRn bus has cycled through all quadrants of all devices, control of the PAEn/PRn will pass to the master device again and so on. The ESYNC of each respective device will operate independently and simply indicate when that respective device has taken control of the bus and is placing its first quadrant on to the PAEn/PRn bus. When operating in single device mode the EXI input must be connected to the EXO output of the same device. In single device mode a token is still required to be passed into the device for accessing the PAEn bus. Please refer to Figure 31, PAEn/PRn Bus - Polled Mode for timing information.
28
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
BYTE ORDER ON INPUT PORT:
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
D8-D0
D35-D27
D26-D18
D17-D9
A
BYTE ORDER ON OUTPUT PORT:
B
Q26-Q18
C
Q17-Q9
D
Q8-
Write to Queue
BM L
IW L
OW L
Q35-Q27 Q0
A
B
C
D
Read from Queue
(a) x36 INPUT to x36 OUTPUT Q35-Q27 Q0 Q26-Q18 Q17-Q9 Q8-
BM H
IW L
OW L
C
Q35-Q27 Q0 Q26-Q18 Q17-Q9
D
Q8-
1st: Read from Queue
A
(b) x36 INPUT to x18 OUTPUT Q35-Q27 BM H IW L OW H Q35-Q27 Q26-Q18 Q17-Q9 Q26-Q18 Q17-Q9
B
2nd: Read from Queue
Q8-Q0
D
Q8-Q0
1st: Read from Queue
C
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
2nd: Read from Queue
B
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
3rd: Read from Queue
A
(c) x36 INPUT to x9 OUTPUT
BYTE ORDER ON INPUT PORT:
4th: Read from Queue
D35-D27
D26-D18
D17-D9
D8-D0
A
D35-D27 D26-D18 D17-D9
B
D8-D0
1st: Write to Queue
C
D
2nd: Write to Queue
BYTE ORDER ON OUTPUT PORT:
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BM H
IW H
OW L
C
D
A
B
Read from Queue
(d) x18 INPUT to x36 OUTPUT
BYTE ORDER ON INPUT PORT:
D35-D27
D26-D18
D17-D9
D8-D0
A
D35-D27 D26-D18 D17-D9 D8-D0
1st: Write to Queue
B
D35-D27 D26-D18 D17-D9 D8-D0
2nd: Write to Queue
C
D35-D27 D26-D18 D17-D9 D8-D0
3rd: Write to Queue
D
4th: Write to Queue
BYTE ORDER ON OUTPUT PORT:
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BM H
IW H
OW H
D
C
B
A
Read from Queue
5904 drw08
(e) x9 INPUT to x36 OUTPUT
Figure 3. Bus-Matching Byte Arrangement
29
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
tRS
MRS
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tRSS
WEN REN
tRSS
SENI
tRSR
tRSS
FSTR, ESTR
tRSS
WADEN, RADEN
tRSS
ID0, ID1, ID2
tRSS
OW, IW, BM
tRSS
FM
HIGH = Looped LOW = Strobed (Direct)
tRSS
MAST
HIGH = Master Device LOW = Slave Device
tRSS
PKT
HIGH = Packet Ready Mode LOW = Almost Empty
tRSS
DFM
HIGH = Default Programming LOW = Serial Programming
tRSS
DF
HIGH = Offset Value is 128 LOW = Offset value is 8
tRSF
FF HIGH-Z if Slave Device
tRSF
OV
LOGIC "0" if Master Device LOGIC "1" if Master Device HIGH-Z if Slave Device
tRSF
PAF
LOGIC "1" if Master Device HIGH-Z if Slave Device
tRSF
PAE HIGH-Z if Slave Device LOGIC "0" if Master Device
tRSF
PAFn
LOGIC "1" if Master Device HIGH-Z if Slave Device
tRSF
PAEn HIGH-Z if Slave Device
tRSF
PR
LOGIC "0" if Master Device LOGIC "1" if Master Device HIGH-Z if Slave Device
tRSF
PRn
LOGIC "1" if Master Device HIGH-Z if Slave Device
tRSF
Qn
LOGIC "1" if OE is LOW and device is Master HIGH-Z if OE is HIGH or Device is Slave
5904 drw09
NOTES: 1. OE can toggle during this period. 2. PRS should be HIGH during a MRS.
Figure 4. Master Reset
30
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
w-2 WCLK tQS WADEN tENS WEN tAS WRADD FF PAF Active Bus PAF-Qx(5) PRS tPRSS RCLK tENS REN tQS RADEN tAS RDADD
Qx
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
w+2 w+3
w-1 tQH
w
w+1
tENS
tAH Qx tWFF tWAF tPAF tPRSS tPRSH
tPRSH tENS
tQH
tAH
tROV OV tRAE PAE tPAE Active Bus PAE-Qx(6) r-2 r-1 r r+1 r+2 r+3
5904 drw10
NOTES: 1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports. 2. The queue must be selected a minimum of 2 clock cycles before the Partial Reset takes place, on both the write and read ports. 3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle. 4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports. 5. The PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag. 6. The PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.
Figure 5. Partial Reset
Master Reset Default Mode DFM = 0
DFM MRS DFM MRS DFM MRS
MQ1
Serial Enable Serial Input
SENI SI SCLK SENO SO SENI SI
MQ2
SENO SO SCLK SENI SI
MQn
SENO SO SCLK
Serial Loading Complete
Serial Clock
5904 drw11
Figure 6. Serial Port Connection for Serial Programming
31
tRSR
1st Device in Chain 1st 2nd nth 1st 2nd nth 1st 2nd nth 2nd Device in Chain Final Device in Chain
MRS
tSCLK tSCKH tSCKL
SCLK
tSENS
SENI (MQ1)
tSDH B11 tSDOP tSDO B21 tSENO tSENOP B22 B2n B81 B82 B8n B12 B1n B21 B22 B2n B81 B82 B8n
tSDS
SI (MQ1)
SO (MQ1)
SENO (MQ1)
tSENO tSENOP
SENO (MQ2)
tSENO
SENO (MQ8)
Programming Complete
WCLK
tQS tQH
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
32
HIGH - Z HIGH - Z
WADEN/ FSTR
tPCWQ tWFF
FF (Slave Device)
tENS
WEN
RCLK
tQS tQH
RADEN/ ESTR
tPCRQ
tROV
OV (Slave Device)
5904 drw12
NOTES: 1. SENI can be toggled during serial loading. Once serial programming of a device is complete, the SENI and SI inputs become transparent. SENI SENO and SI SO. 2. DFM is LOW during Master Reset to provide Serial programming mode, DF is don't care. 3. When SENO of the final device is LOW no further serial loads will be accepted. 4. n = 19+(Qx72); where Q is the number of queues required for the IDT72V51546/72V51556. 5. This diagram illustrates 8 devices in expansion. 6. Programming of all devices must be complete (SENO of the final device is LOW), before any write or read port operations can take place, this includes queue selections.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 7. Serial Programming
MRS
1st Device in Chain 2nd 1st 1st 3rd nth 2nd 2nd nth nth 2nd Device in Chain Final Device in Chain
1st
WCLK
tSENO
SENO (MQ1)
tSENO
SENO (MQ2)
tSENO
SENO (MQ8)
tQS
Programming Complete
tQH
WADEN/ FSTR
tPCWQ tWFF
FF (Slave Device) HIGH - Z
tENS
WEN
RCLK
tQS tQH
RADEN/ ESTR
tPCRQ
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
33
HIGH - Z Master Reset Default Mode DFM = 1
DFM MRS
tROV
OV (Slave Device)
DFM
MRS
DFM
MRS
MQ1
Serial Enable (can be tied LOW)
SENI SI SENO SO WCLK X SENI SI
MQ2
SENO SO WCLK X SENI SI
MQn
SENO SO WCLK X
Serial Loading Complete
WCLK
NOTES: 1. This diagram illustrates multiple devices connected in expansion. The SENO of the final device in a chain is the "programming complete" signal. 2. SENI of the first device in the chain can be held LOW 3. The SENO of a device should connect to the SENI of the next device in the chain. The final device SENO is used to indicate programming complete. 4. When Default Programming is complete the SENO of the final device will go LOW. 5. SCLK is not used and can be tied LOW. 6. Programming of all devices must be complete (SENO of the final device is LOW), before any write or read port operations can take place, this includes queue selections.
Serial Port Connection for Default Programming
5904 drw12a
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 8. Default Programming
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
*J*
WCLK tENS tENH
No Writes Queue Full
WEN tAS tAH
tAS
tAH
WRADD
Qx
tQS tQH
Qy
tQS
tQH
WADEN tDS tDS tDH tDS tDH tDH tDS tDH
Din
QX WD
2
Qy WDtWFF tWFF tWFF tWFF
tWFF
WD-1 Qy
Qy WD
FF tSKEW
1
Previous Q Status
RCLK tENS
REN tQS tQH
RADEN tAS tAH
RDADD tA
Previous Q, Word, W
PFT
Qy
tA
Previous Q, W+1 Qy, W0
PFT
tA
Qy, W1
tA
Qy, W2
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
34
*AA* *BB* *CC* *DD *
Qout
*EE*
*FF*
5904 drw13
NOTE: OE is active LOW. Cycle: *A* Queue, Qx is selected on the write port. The FF flag is providing status of a previously selected queue, within the same device. *AA* Queue, Qy is selected for read operations. *B* The FF flag output updates to show the status of Qx, it is not full. *BB* Word W+1 is read from the previous queue regardless of REN due to FWFT. *C* Word, Wd is written into Qx. This causes Qx to go full. *CC* Word, W0 is read from Qy regardless of REN, this is due to the FWFT effect. *D* Queue, Qy is selected within the same device as Qx. A write to Qx cannot occur on this cycle because it is full, FF is LOW. *DD* No reads occur, REN is HIGH. *E* Again, a write to Qx cannot occur on this cycle because it is full, FF is LOW. The FF flag updates after time tWFF to show that queue, Qy is not full. *EE* Word, W1 is read from Qy, this causes Qy to go "not full", FF flag goes HIGH after time, tSKEW1 + tWFF. Note, if tSKEW1 is violated the time FF HIGH will be: tSKEW1 + WCLK + tWFF. *F* Word, Wd-2 is written into Qy. *FF* Word, W2 is read from Qy. *G* Word, Wd-1 is written into Qy. *H* Word, Wd is written into Qy, this causes Qy to go full, FF goes LOW. *I* No writes occur to Qy. *J* Qy goes "not full" based on reading word W1 from Qy on cycle *EE*.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 9. Write Queue Select, Write Operation and Full Flag Operation
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
WCLK
tENS tENH
WEN tDS Dn
W1
tDH
tDS
W2
tDH
tDS
W3
tDH
tSKEW1 RCLK
1 2
tENS
REN tA Qout
Last Word Read Out of Queue W1 Qy FWFT
tA
W2 Qy FWFT
tA
W3 Qy
tROV
tROV
OV
5904 drw13a
NOTES: 1. Qy has previously been selected on both the write and read ports. 2. OE is LOW. 3. The First Word Latency = tSKEW1 + RCLK + tA. If tSKEW1 is violated an additional RCLK cycle must be added.
Figure 10. Write Operations & First Word Fall Through
35
No Write
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
*J*
WCLK tENS tENH tENS tENH
WEN tAS tAS tAH tAH
tAS
tAH
WRADD
D1 Q27
tQS
Addr=001 tQH 00101
D1 Q5
tQS tQH
D2 Q9
tQS
Addr=001 tQH 11011
WADEN tDS tDH tDS tDH
Din
WD
D1 Q27 tFFLZ tWFF tWFF tWFF tWFF D1 Q5
WD
tFFHZ
HIGH-Z
HIGH-Z FF (Device 1)
tFFHZ
HIGH-Z
tFFLZ tSKEW1
1 2
FF (Device 2)
RCLK tAS tAH
RDADD
D1 Q5
tQS tQH
RADEN tA
Previous Q WX-1 Previous Q WX
PFT
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
36
*AA* *BB*
tA
D1-Q5 Word W0
PFT
5904 drw14
Qout
NOTE: 1. REN = HIGH. Cycle: *A* Queue, Q27 of device 1 is selected on the write port. The FF flag of device 1 is in High-Impedance, the write port of device 2 was previously selected. WEN is HIGH so no write occurs. *AA* Queue, Q5 of device 1 is selected on the read port. *B* The FF flag of device 2 goes to High-Impedance and the FF flag of device 1 goes to Low-Impedance, logic HIGH indicating that D1 Q27 is not full. WEN is HIGH so no write occurs. *BB* Word, Wx is read from the previously selected queue, (due to FWFT). *C* Word, Wd is written into Q27 of D1. This write operation causes Q27 to go full, FF goes LOW. *CC* The first word from Q5 of D1 selected on cycle *AA* is read out, this occurred regardless of REN due to FWFT. This read caused Q5 to go not full, therefore the FF flag will go HIGH after: tSKEW1 + tWFF. Note if tSKEW1 is violated the time to FF flag HIGH is tSKEW1 + WLCK + tWFF. *D* Queue, Q5 of device 1 is selected on the write port. No write occurs on this cycle. *E* The FF flag updates to show the status of D1 Q5, it is not full, FF goes HIGH. *F* Word, Wd is written into Q5 of D1. This causes the queue to go full, FF goes LOW. *G* No write occurs regardless of WEN, the FF flag is LOW preventing writes. *H* The FF flag goes HIGH due to the read from Q5 of D1 on cycle *CC*. (This read is not an enabled read, it is due to the FWFT operation). *I* Queue, Q9 of device 2 is selected on the write port. *J* The FF flag of device 1 goes to High-Impedance, this device was deselected on the write port on cycle *I*. The FF flag of device 2 goes to Low-Impedance and provides status of Q9 of D2.
*CC*
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 11. Full Flag Timing in Expansion Mode
*A*
1 2
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
RCLK tENH tENS
tENS
REN tAS tAH tAS tAH
RDADD
QF
tQS tQH tQS tQH
QG
RADEN tA tA tA tA tA
tA
QOUT
QP Wn-3 Previous Q, QP Wn-1
PFT PFT
QP Wn-2 QP Wn QF W0 QF W1
QF W2
tROV
Previous Q
OV
5904 drw15
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
37
Cycle: *A* Word Wn-3 is read from a previously selected queue Qp on the read port. *B* Wn-2 is read. *C* Reads are disabled, Wn-1 remains on the output bus. *D* A new queue, QF is selected for read operations. *E* Due to the First Word Fall Through (FWFT) effect, a read from the previous queue Qp will take place, Wn from Qp is placed onto the output bus regardless of REN. *F* The next word available in the new queue, QF-W0 falls through to the output bus, again this is regardless of REN. *G* A new queue, QG is selected for read operations. (This queue is an empty queue). Word, W1 is also read from QF. *H* Word, W1 is read from QF. This occurs regardless of REN due to FWFT. *I* Word W2 from QF remains on the output bus because QG is empty. The Output Valid Flag, OV goes HIGH to indicate that the current word is not valid, i.e. QG is empty. W2 is the last word in QG.
Figure 12. Read Queue Select, Read Operation
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
*A* *B* *C* *D* *E* *F* *G*
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
*H* *I*
RCLK tENS REN tAS RDADD tQS RADEN tA Qout (Device 1)
HIGH-Z OV (Device 1)
tAH
tAS
tAH
D1 Q30
tQH tQS
D1 Q15
tQH
tA
tA
tA
tOLZ
D1 Q30 WD Last Word
tOVLZ tROV tROV
D1 Q15
PFT We-1
D1 Q15 We Last Word
tROV
tROV
W0 Q15 D1
tOVHZ OV (Device 2) WCLK tENS WEN tAS WRADD tQS WADEN tDS Din tDH tAH tENH tSKEW1
D1 Q15
tQH
D1 Q15 W0
5904 drw16
Cycle: *A* Queue 30 of Device 1 is selected for read operations. The OV is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control of Qout bus, its Qout outputs are in Low-Impedance. This diagram only shows the Qout outputs of device 1. (Reads are disabled). *B* Reads are now enabled. A word from the previously selected queue of Device 2 will be read out. *C* The Qout of Device 1 goes to Low-Impedance and word Wd is read from Q30 of D1. This happens to be the last word of Q30. Device 2 places its Qout outputs into High-Impedance, device 1 has control of the Qout bus. The OV flag of Device 2 goes to High-Impedance and Device 1 takes control of OV. The OV flag of Device 1 goes LOW to show that Wd of Q30 is valid. *D* Queue 15 of device 1 is selected for read operations. The last word of Q30 was read on the previous cycle, therefore OV goes HIGH to indicate that the data on the Qout is not valid (Q30 was read to empty). Word, Wd remains on the output bus. *E* The last word of Q30 remains on the Qout bus, OV is HIGH, indicating that this word has been previously read. *F* The next word (We-1), available from the newly selected queue, Q15 of device 1 is now read out. This will occur regardless of REN, 2 RCLK cycles after queue selection due to the FWFT operation. The OV flag now goes LOW to indicate that this word is valid. *G* The last word, We is read from Q15, this queue is now empty. *H* The OV flag goes HIGH to indicate that Q15 was read to empty on the previous cycle. *I* Due to a write operation the OV flag goes LOW and data word W0 is read from Q15. The latency is: tSKEW1 + 1*RCLK + tROV.
Figure 13. Output Valid Flag Timing (In Expansion Mode)
38
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
*A* *B* *C* *D* *E* *F* *G* *H*
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
*I* *J*
RCLK tENS REN tAS RDADD tQS RADEN tA QOUT OV
5904 drw17
tENH tAH tAS tAH
tENS
tENH
Qn
tQH tQS
QP
tQH
tA
tA
tA
tA
tA
QP WD
QP WD+1
QP WD+2
Qn WX
Qn WX+1
QP WD+3
QP WD+4
Cycle: *A* Word Wd+1 is read from the previously selected queue, Qp. *B* Reads are disabled, word Wd+1 remains on the output bus. *C* A new queue, Qn is selected for read port operations. *D* Due to FWFT operation Word, Wd+2 of Qp is read out regardless of REN. *E* The next available word Wx of Qn is read out regardless of REN, 2 RCLK cycles after queue selection. This is FWFT operation. *F* The queue, Qp is again selected. *G* Word Wx+1 is read from Qn regardless of REN, this is due to FWFT. *H* Word Wd+3 is read from Qp, this read occurs regardless of REN due to FWFT operation. *I* Word Wd+4 is read from Qp. *J* Reads are disabled on this cycle, therefore no further reads occur.
Figure 14. Read Queue Selection with Reads Disabled
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
RCLK tENS REN tAS RDADD tQS RADEN QA tQH tQS tAH tAS QB tQH tAH tENH tENS
OE tOLZ tOE Previous Data in O/P Register tROV OV
5904 drw18
tA QA W0
PFT
tA QA W1
tA QA W2
tA QA W3
tA QA W4 tROV
tOHZ
No Read QB is Empty
Qout
NOTES: 1. The Output Valid flag, OV is HIGH therefore the previously selected queue has been read to empty. The Output Enable input is Asynchronous, therefore the Qout output bus will go to Low-Impedance after time tOLZ. The data currently on the output register will be available on the output after time tOE. This data is the previous data on the output register, this is the last word read out of the previous queue. 2. In expansion mode the OE inputs of all devices should be connected together. This allows the output busses of all devices to be High-Impedance controlled. Cycle: *A* Queue A is selected for reads. No data will fall through on this cycle, the previous queue was read to empty. *B* No data will fall through on this cycle, the previous queue was read to empty. *C* Word, W0 from Qa is read out regardless of REN due to FWFT operation. The OV flag goes LOW indicating that Word W0 is valid. *D* Reads are disabled therefore word, W0 of Qa remains on the output bus. *E* Reads are again enabled so word W1 is read from Qa. *F* Word W2 is read from Qa. *G* Queue, Qb is selected on the read port. This queue is actually empty. Word, W3 is read from Qa. *H* Word, W4 falls through from Qa. *I* Output Valid flag, OV goes HIGH to indicate that Qb is empty. Data on the output port is no longer valid. Output Enable is taken HIGH, this is Asynchronous so the output bus goes to High-Impedance after time, tOHZ.
Figure 15. Read Queue Select, Read Operation and OE Timing
39
A
1 tAS tAH 2 1 2
B
C(1) D E F G H J K
I(1)
WCLK
tAS
tAH
WRADD
QC
QA
QB
WADEN
tDH tDS tDH
tDS
Din
QA Data QB TSOP
QA TEOP QC TSOP
QA Dummy QB Data QB Data QB TEOP
QB Dummy
QC Data
QC Data
WEN
TEOP
(D35)
TSOP
5904 drw19
(D34)
NOTE: 1. Do not Write an SOP or EOP on "C" or "I". A filler word is needed.
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
40
Figure 16. Writing in Packet Mode during a Queue change
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
A
1 tAH tAS tAH 2 1 2
B
C
D(1) E F G H I J
K(1)
RCLK
tAS
RDADD
QC
QA
QB
RADEN
tA tA tA tA tA tA tA tA
Qout
QA Data QB RSOP
QA Data QB Data QB REOP
QA REOP
QA "Dummy" QB Data
QB "Dummy"
QC RSOP
REN
REOP
(Q35)
RSOP
5904 drw20
(Q34)
NOTE: 1. Do not Read an SOP or EOP on "D" or "K". A filler word is needed.
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
41
Figure 17. Reading in Packet Mode during a Queue change
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
*A* *B* *C*
WCLK
tENH
tENS
WEN
tDH
tDS
D0-D31 P1Wn-3
tDH
P1Wo P1Wn-2 P1Wn-1 P1Wn
tDS
TSOP (D34)
tDS tDH
TEOP (D35)
tDH tDS tDH tDS tDH
tDS
TAEOP/ TMOD1 (D33)
tDH tDS tDH
tDS
TMOD2 (D32)
tSKEW4 tSKEW5
RCLK
tPR
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
42
Last Word Read Out
PR
tRO
V
OV
tA
P1Wo
5904 drw21
Qn
NOTES: 1. REN is HIGH. 2. If tSKEW4 is violated PR may take one additional RCLK cycle. 3. If tSKEW5 is violated the OV may take one additional RCLK cycle. 4. PR will always go LOW on the same cycle or 1 cycle ahead of OV going LOW, (assuming the last word of the packet is the last word in the queue). 5. In Packet mode, words cannot be read from a queue until a complete packet has been written into that queue, regardless of REN.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 18. Data Input (Transmit) Packet Mode of Operation
*A* *B* *C* *D*
*E*
RCLK
tENS
REN
tPR
PR
tA tA
RSOP (Q34)
REOP (Q35)
tA tA tA tA
tA
tA
Q0-Q31 P1Wo P1W1 P1W2 P1Wn-3
P1Wn-2
P1Wn-1
P1Wn
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
43
RAEOP/ RMOD1 (Q33)
RMOD2 (Q32)
tRO
V
OV
5904 drw22
NOTES: 1. In Packet mode, words cannot be read from a queue until a complete packet has been written into that queue, regardless of REN. 2. The PR flag will go HIGH on cycle *C* regardless of REN. 3. The OV flag will go HIGH (preventing further reads), when the last complete packet has been read out. If there is a partial packet (an incomplete packet) in the queue the OV flag will remain HIGH until further writes have completed the packet.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 19. Data Output (Receive) Packet Mode of Operation
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
NULL QUEUE SELECT *A* SELECT NEW QUEUE *D*
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
*B*
*C*
*E*
*F*
RCLK
tAS
RDADD 00100000
tAH
tAS
00000100
tAH
tQS
RADEN
tQH
tQS
tQH
tENH
REN
tENS tA
Q1 Wn-1 Q1 Wn
tA
Qout Q1 Wn-3 Q1 Wn-2
tA
tA
Q4 W0
tROV
OV
tROV
FWFT
5904 drw23
NOTES: 1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words from that queue. 2. Please see Figure 21, Null Queue Flow Diagram. Cycle: *A* Null Q of device 0 (33rd queue) is selected, when word Wn-1 from previously selected Q1 is read. *B* REN is HIGH and Wn (Last Word of the Packet) of Q1 is pipelined onto the O/P register. Note: *B* and *C* are a minimum 2 RCLK cycles between Q selects. *C* The Null Q is seen as an empty Queue on the read side, therefore Wn of Q1 remains in the O/P register and OV goes HIGH. *D* A new Q, Q4 is selected and the 1st word of Q4 will fall through present on the O/P register on cycle *F*.
Figure 20. Read Operation and Null Queue Select
*A*
Queue 1 Memory
*B*
Null Queue
*C*
Null Queue
*D*
Null Queue
*E*
Queue 4 Memory
*F*
Queue 4 Memory
Q1 Wn O/P Reg. Qn Wn-1
Q1 Wn O/P Reg. Q1 Wn
Q1 Wn O/P Reg. Q1 Wn
Q1 Wn O/P Reg. Q1 Wn
Q4 W0 O/P Reg. Q1 Wn
Q4 W1 O/P Reg. Q4 W0
5904 drw24
Figure 21. Null Queue Flow Diagram
44
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
*A* *B* *C* *D*
1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
*E*
2
*F*
WCLK tENS WEN tAS WRADD tQS WADEN tDS Din tDH tAH tAS tENH
tAH
D1 Q5
tQH tQS
D1 Q9
tQH
WD-m D1 Q5
tAFLZ tWAF tWAF
HIGH-Z PAF (Device 1)
tFFHZ PAF (Device 2)
Cycle: *A* Queue 5 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance. *B* No write occurs. *C* Word, Wd-m is written into Q5 causing the PAF flag to go from HIGH to LOW. The flag latency is 2 WCLK cycles + tWAF. *D* Queue 9 if device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 2 WCLK + tWAF latency. *E* The PAF flag goes LOW based on the write 2 cycles earlier. *F* The PAF flag goes HIGH due to the queue switch to Q9.
5904 drw25
Figure 22. Almost Full Flag Timing and Queue Switch
tCLKL
WCLK
tCLKL
1 2 1
tENS
WEN
tENH
tWAF
PAF
D - (m+1) words in Queue D - m words in Queue
tWAF tSKEW2
D-(m+1) words in Queue
RCLK
tENS
REN
tENH
5904 drw26
NOTE: 1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read from at the almost full boundary. Flag Latencies: Assertion: 2*WCLK + tWAF De-assertion: tSKEW2 + WCLK + tWAF If tSKEW2 is violated there will be one extra WCLK cycle.
Figure 23. Almost Full Flag Timing
45
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
*A* *B* *C* *D* *E*
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
*F* *G*
RCLK
REN
HIGH
tAS RDADD tQS RADEN
tAH
tAS
tAH
D1 Q30
tQH tQS
D1 Q15
tQH
tOLZ Qout
HIGH-Z
tA
tA
tA
tA
D1 Q30 Wn
tAELZ
D1 Q30 Wn+1
tRAE
D1 Q15 W0
tRAE
D1 Q15 W1
HIGH-Z PAE (Device 1)
tAEHZ PAE (Device 2)
HIGH-Z
5904 drw27
Cycle: *A* Queue 30 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance. *B* No read occurs. *C* The PAE flag output now switches to device 1. Word, Wn is read from Q30 due to the FWFT operation. This read operation from Q30 is at the almost empty boundary, therefore PAE will go LOW 2 RCLK cycles later. *D* Q15 of device 1 is selected. *E* The PAE flag goes LOW due to the read from Q30 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation. *F* Word, W0 is read from Q15 due to the FWFT operation. The PAE flag goes HIGH to show that Q15 is not almost empty.
Figure 24. Almost Empty Flag Timing and Queue Switch
tCLKH WCLK
tCLKL tENS tENH
WEN PAE
n+1 words in Queue n+2 words in Queue
n+1 words in Queue
tSKEW2 RCLK
tRAE
1
tRAE
2
tENS REN
tENH
5904 drw25
NOTE: 1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read from at the almost empty boundary. Flag Latencies: Assertion: 2*RCLK + tRAE De-assertion: tSKEW2 + RCLK + tRAE If tSKEW2 is violated there will be one extra RCLK cycle.
Figure 25. Almost Empty Flag Timing
46
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
RCLK tQS
Device 1 Quadrant 2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tQH
001xxx10
tQS
Device 1 Quadrant 3
tQH
tQS
Device 1 Quadrant 0
tQH
RDADD tSTS ESTR
001xxx11
001xxx00
tSTH
tSTS
tSTH
tPAE PAEn/ PRn
Device 1 Quadrant 2
tPAE
Device 1 Quadrant 3
tPAE
Device 1 Quadrant 0
5904 drw29
NOTES: 1. Quadrants can be selected on consecutive cycles. 2. On an RCLK cycle that the ESTR is HIGH, the RADEN input must be LOW. 3. There is a latency of 1 RCLK for the PAEn bus to switch.
Figure 26. PAEn/PRn - Direct Mode - Quadrant Selection
WCLK tQS
Device 1 Quadrant 1
tQH
001xxx01
tQS
Device 1 Quadrant 3
tQH
tQS
Device 1 Quadrant 2
tQH
WRADD tSTS FSTR
001xxx11
001xxx10
tSTH
tSTS
tSTH
tPAF PAFn
Device 1 Quadrant 1
tPAF
Device 1 Quadrant 3
tPAF
Device 1 Quadrant 2
5904 drw30
NOTES: 1. Quadrants can be selected on consecutive cycles. 2. On a WCLK cycle that the FSTR is HIGH, the WADEN input must be LOW. 3. There is a latency of 1 WCLK for the PAFn bus to switch.
Figure 27. PAFn - Direct Mode - Quadrant Selection
47
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
*A* WCLK tQS WADEN tSTS FSTR tENS WEN tAS WRADD Dn tAH D5Q24 100 11000 tDH tAS tDS tDH Wn D5 Q24 tSKEW3 RCLK tQS RADEN tSTS ESTR tENS REN tAS RDADD D5Q24 100 11000 Wa D5 Q17 tAH tAS
D5 quad 4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
*E* tQH tSTH *F*
*B* 1 tQH
*C* 2 tQS
*D*
tENH
tENS
tENH
tAH
tAS
D4 quad 3
tAH
tDS
D3Q8 011 01000 Wn+1 D5Q24
100 xxx10 Wx D3 Q8 2
Wp Wp+1 Writes to Previous Q
tQH
1
tSTH tENH
tAH 101 xxx11 tA Wa+1 D5 Q17
tA
Device 5 -Qn Prev PAEn Device 5 PAEn Bus PAEn
tA Wy D5 Q24
tA Wy+1 D5 Q24 tPAEHZ xxxx xxx1 D5Quad 4
tA Wy+2 D5 Q24 tPAE
Wy+3 D5 Q24
Previous value loaded on to PAE bus tPAEZL xxxx xxx0 D5Quad4 xxxx xxx0 D5Quad4 tRAE
Previous value loaded on to PAE bus tRAE tRAE
xxxx xxx1 D5Quad 4 D5 Q24 status
Device 5 PAE
D5 Q17 Status *AA* *BB* *CC*
5904 drw31
*DD*
*EE*
*FF*
Cycle: *A* Queue 24 of Device 5 is selected for write operations. Word, Wp is written into the previously selected queue. *AA* Queue 24 of Device 5 is selected for read operations. A quadrant from another device has control of the PAEn bus. The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device. *B* Word Wp+1 is written into the previously selected queue. *BB* Word, Wa+1 is read from Q17 of D5, due to FWFT operation. *C* Word, Wn is written into the newly selected queue, Q24 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time, tSKEW3 + RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added. *CC* Word, Wy from the newly selected queue, Q24 will be read out due to FWFT operation. Quadrant 4 of Device 5 is selected on the PAEn bus. Q24 of device 5 will therefore have is PAE status output on PAE[0]. There is a single RCLK cycle latency before the PAEn bus changes to the new selection. *D* Queue 8 of Device 3 is selected for write operations. Word Wn+1 is written into Q24 of D5. *DD* The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and quadrant 4 is placed onto the outputs. The device of the previously selected quadrant now places its PAEn outputs into High-Impedance to prevent bus contention. Word, Wy+1 is read from Q24 of D5. The discrete PAE flag will go HIGH to show that Q24 of D5 is not almost empty. Q24 of device 5 will have its PAE status output on PAE[0]. *E* No writes occur. *EE* Word, Wy+2 is read from Q24 of D5. *F* Quadrant 3 of device 4 is selected on the write port for the PAFn bus. Word, Wx is written into Q8 of D3. *FF* The PAEn bus updates to show that Q24 of D5 is almost empty based on the reading out of word, Wy+1. The discrete PAE flag goes LOW to show that Q24 of D5 is almost empty based on the reading of Wy+1.
Figure 28. PAEn - Direct Mode, Flag Operation
48
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
*A* RCLK tQS RADEN tSTS ESTR REN tAS RDADD OE tOLZ Qout WX Prev. Q tA WX +1 Prev. Q tSKEW3 WCLK tSTS FSTR tAS WRADD WEN tQS WADEN tDS tDH tDS tDH Wy+1 Word Wy D0 Q31 D0 Q31 tPAF 0xxx xxxx 0xxx xxxx D0Quad4 D0Quad4 tQH
D0 quad4
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
*E * tQS tQH *F * *G*
*B* tQH
*C*
*D*
tSTH
tAH D0Q31 000 11111
tAS
D7 quad 1
tAH 111 xxx00 tA WD-M+1 D0 Q31 D6Q2 110 00010
tA WD - M + 2 D0 Q31
tA W0 D6 Q2
1 tSTH tAH tAS
D0 Q31
2
tAH tENS tENH
000 xxx11
tDS
Din tPAFLZ Device 0 PAFn
HIGH-Z
tDH Wy+2 D0 Q31 tPAF D0Quad4 0xxx xxxx D0Quad40xxx xxxx
D0Quad4 DXQuad y DXQuad y HIGH - Z *AA* *BB* *CC* D0Quad4 tPAFHZ
1xxx xxxx 1xxx xxxx HIGH-Z
Bus PAFn Prev. PAFn Device 0 PAF
tPAFLZ
tWAF
5904 drw32
*DD*
*EE*
*FF*
Cycle: *A* Queue 31 of device 0 is selected for read operations. The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance. *AA* Quadrant 4 of device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected quadrant, Quad Y of device X. *B* Word, Wx+1 is read out from the previous queue due to the FWFT effect. *BB* Queue 31 of device 0 is selected on the write port. The PAFn bus is updated with the quadrant selected on the previous cycle, D0 Quad 4. PAF[7] is LOW showing the status of queue 31. The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance. *C* A new quadrant, Quad 1 of Device 7 is selected for the PAFn bus. Word, Wd-m+1 is read from Q31 D0 due to the FWFT operation. This read is at the PAFn boundary of queue D0 Q31. This read will cause the PAF[7] output to go from LOW to HIGH (almost full to not almost full), after a delay tSKEW3 + WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle. *CC* PAFn continues to show status of Quad4 D0. *D* No read operations occur, REN is HIGH. *DD* PAF[7] goes HIGH to show that D0 Q31 is not almost empty due to the read on cycle *C*. The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance. Word, Wy is written into D0 Q31. *E* Queue 2 of Device 6 is selected for write operations. *EE* Word, Wy+1 is written into D0 Q31. *F* Word, Wd-m+2 is read out due to FWFT operation. *FF* PAF[7] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q31 of D0 to again go almost full. Word, Wy+2 is written into D0 Q31. *G* Word, W0 is read from Q0 of D6, selected on cycle *E*, due to FWFT.
Figure 29. PAFn - Direct Mode, Flag Operation
49
WCLK tFSYNC tFSYNC tFSYNC
tFSYNC
FSYNC0 tFXO tFXO
(MASTER)
FXO0 / tFSYNC tFSYNC
FXI1
FSYNC1 tFXO tFXO
(SLAVE)
FXO1 / tFSYNC tFSYNC
FXI2
FSYNC2 tFXO tFXO
(SLAVE)
FXO2 / tPAF
D0Quad1 D0Quad4 D1Quad1 D1Quad4 D0Quad2 D0Quad3 D1Quad2 D1Quad3 D2Quad1
FXI0 tPAF tPAF tPAF tPAF tPAF tPAF tPAF tPAF tPAF
D2Quad2
tPAF
D2Quad3
tPAF
D2Quad4
tPAF
D0Quad1
tPAF
D0Quad2
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PAFn
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
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NOTE: 1. This diagram is based on 3 devices connected in expansion mode.
Figure 30. PAFn Bus - Polled Mode
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RCLK tESYNC tESYNC tESYNC
tESYNC
ESYNC0 tEXO tEXO
EXO0 / tESYNC tESYNC
EXI1
ESYNC1 tEXO tEXO
EXO1 / tESYNC tESYNC
EXI2
ESYNC2 tEXO tEXO
EXO2 / tPAE tPAE
D0Quad4 D1Quad1 D1Quad2 D1Quad4 D1Quad3 D2Quad1
EXI0 tPAE tPAE tPAE tPAE
D0Quad3
tPAE
D0Quad2
tPAE
tPAE
tPAE
D2Quad2
tPAE
D2Quad3
tPAE
D2Quad4
tPAE
D0Quad1
tPAE
D0Quad2
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PAEn
D0Quad1
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
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NOTE: 1. This diagram is based on 3 devices connected in expansion mode.
Figure 31. PAEn/PRn Bus - Polled Mode
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
Serial Programming Data Input Serial Enable SENI Data Bus Write Clock Write Enable Write Queue Select Write Address WADEN Full Strobe Programmable Almost Full Full Sync1 Full Flag Almost Full Flag Serial Clock FSTR PAFn FSYNC FF PAF SCLK SENO SO FXO EXO D0-D35 WCLK WEN WRADD SI FXI EXI
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Output Data Bus Q0-Q35 RCLK REN RDADD Read Clock Read Enable Read Queue Select Read Address Empty Strobe Programmable Almost Empty Empty Sync 1 Output Valid Flag Almost Empty Flag Packet Reads
DEVICE 1
RADEN ESTR PAEn ESYNC OV PAE PR
SENI D0-D35
SI
FXI
EXI Q0-Q35
WCLK WEN WRADD WADEN FSTR Full Sync2 PAFn FSYNC FF PAF SCLK SENO SO FXO EXO
RCLK REN RDADD RADEN
DEVICE 2
ESTR PAEn ESYNC OV PAE PR
Empty Sync 2
SENI
SI
FXI
EXI
D0-D35
Q0-Q35
WCLK WEN WRADD WADEN FSTR PAFn FSYNC FF PAF SCLK SENO FXO EXO
RCLK REN RDADD RADEN ESTR PAEn ESYNC OV PAE PR
DEVICE n
Full Sync n
Empty Sync n
DONE
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NOTES: 1. If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO outputs are DNC (Do Not Connect). 2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.
Figure 32. Multi-Queue Expansion Diagram
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
JTAG INTERFACE
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V51546/72V51556 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. Note that IDT provides appropriate Boundary Scan Description Language program files for these devices.
The Standard JTAG interface consists of four basic elements: Test Access Port (TAP) * TAP controller * Instruction Register (IR) * Data Register Port (DR) * The following sections provide a brief description of each element. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). The Figure below shows the standard Boundary-Scan Architecture
DeviceID Reg. Boundary Scan Reg. Bypass Reg.
Mux
TDO TDI
T A
TMS TCLK TRST
P TAP Controller
clkDR, ShiftDR UpdateDR
Instruction Decode clklR, ShiftlR UpdatelR Instruction Register
Control Signals
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Figure 33. Boundary Scan Architecture
TEST ACCESS PORT (TAP) The Tap interface is a general-purpose port that provides access to the internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST) and one output port (TDO).
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THE TAP CONTROLLER The Tap controller is a synchronous finite state machine that responds to TMS and TCLK signals to generate clock and control signals to the Instruction and Data Registers for capture and update of data.
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
Test-Logic Reset 0 1 1 1 SelectIR-Scan 1 0 Capture-IR 0 Shift-IR 1 1 Exit1-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0
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0
Run-Test/ Idle
SelectDR-Scan 0 1 Capture-DR 00 Shift-DR 1
0
Input = TMS
Exit1-DR 00 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0
1
0
NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS). 3. TAP controller must be reset before normal Queue operations can begin.
Figure 34. TAP Controller State Diagram
Refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1) for the full state diagram. All state transitions within the TAP controller occur at the rising edge of the TCLK pulse. The TMS signal level (0 or 1) determines the state progression that occurs on each TCLK rising edge. The TAP controller takes precedence over the Queue and must be reset after power up of the device. See TRST description for more details on TAP controller reset. Test-Logic-Reset All test logic is disabled in this controller state enabling the normal operation of the IC. The TAP controller state machine is designed in such a way that, no matter what the initial state of the controller is, the TestLogic-Reset state can be entered by holding TMS at high and pulsing TCK five times. This is the reason why the Test Reset (TRST) pin is optional. Run-Test-Idle In this controller state, the test logic in the IC is active only if certain instructions are present. For example, if an instruction activates the self test, then it will be executed when the controller enters this state. The test logic in the IC is idles otherwise. Select-DR-Scan This is a controller state where the decision to enter the Data Path or the Select-IR-Scan state is made. Select-IR-Scan This is a controller state where the decision to enter the Instruction Path is made. The Controller can return to the Test-Logic-Reset state other wise.
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Capture-IR In this controller state, the shift register bank in the Instruction Register parallel loads a pattern of fixed values on the rising edge of TCK. The last two significant bits are always required to be "01". Shift-IR In this controller state, the instruction register gets connected between TDI and TDO, and the captured pattern gets shifted on each rising edge of TCK. The instruction available on the TDI pin is also shifted in to the instruction register. Exit1-IR This is a controller state where a decision to enter either the PauseIR state or Update-IR state is made. Pause-IR This state is provided in order to allow the shifting of instruction register to be temporarily halted. Exit2-DR This is a controller state where a decision to enter either the ShiftIR state or Update-IR state is made. Update-IR In this controller state, the instruction in the instruction register is latched in to the latch bank of the Instruction Register on every falling edge of TCK. This instruction also becomes the current instruction once it is latched. Capture-DR In this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of TCK. Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and Update-IR states in the Instruction path.
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
THE INSTRUCTION REGISTER The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The Instruction is used to select the test to be performed, or the test data register to be accessed, or both. The instruction shifted into the register is latched at the completion of the shifting process when the TAP controller is at UpdateIR state. The instruction register must contain 4 bit instruction register-based cells which can hold instruction data. These mandatory cells are located nearest the serial outputs they are the least significant bits. TEST DATA REGISTER The Test Data register contains three test data registers: the Bypass, the Boundary Scan register and Device ID register. These registers are connected in parallel between a common serial input and a common serial data output. The following sections provide a brief description of each element. For a complete description, refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). TEST BYPASS REGISTER The register is used to allow test data to flow through the device from TDI to TDO. It contains a single stage shift register for a minimum length in serial path. When the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of TCLK when the TAP controller is in the Capture-DR state. The operation of the bypass register should not have any effect on the operation of the device in response to the BYPASS instruction. THE BOUNDARY-SCAN REGISTER The Boundary Scan Register allows serial data TDI be loaded in to or read out of the processor input/output ports. The Boundary Scan Register is a part of the IEEE 1149.1-1990 Standard JTAG Implementation. THE DEVICE IDENTIFICATION REGISTER The Device Identification Register is a Read Only 32-bit register used to specify the manufacturer, part number and version of the processor to be determined through the TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72V51546/72V51556, the Part Number field contains the following values: Device IDT72V51546 IDT72V51556 Part# Field (HEX) 0x44C 0x44D
JTAG INSTRUCTION REGISTER The Instruction register allows instruction to be serially input into the device when the TAP controller is in the Shift-IR state. The instruction is decoded to perform the following: Select test data registers that may operate while the instruction is * current. The other test data registers should not interfere with chip operation and the selected data register. Define the serial test data register path that is used to shift data between * TDI and TDO during data register scanning. The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode 16 different possible instructions. Instructions are decoded as follows. Hex Value 00 01 02 04 0F Instruction EXTEST SAMPLE/PRELOAD IDCODE HIGH-IMPEDANCE BYPASS Function Select Boundary Scan Register Select Boundary Scan Register Select Chip Identification data register JTAG Select Bypass Register
JTAG INSTRUCTION REGISTER DECODING
The following sections provide a brief description of each instruction. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). EXTEST The required EXTEST instruction places the IC into an external boundarytest mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register is accessed to drive test data off-chip via the boundary outputs and receive test data off-chip via the boundary inputs. As such, the EXTEST instruction is the workhorse of IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts and of logic cluster function. IDCODE The optional IDCODE instruction allows the IC to remain in its functional mode and selects the optional device identification register to be connected between TDI and TDO. The device identification register is a 32-bit shift register containing information regarding the IC manufacturer, device type, and version code. Accessing the device identification register does not interfere with the operation of the IC. Also, access to the device identification register should be immediately available, via a TAP data-scan operation, after power-up of the IC or after the TAP has been reset using the optional TRST pin or by otherwise moving to the Test-Logic-Reset state. SAMPLE/PRELOAD The required SAMPLE/PRELOAD instruction allows the IC to remain in a normal functional mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register can be accessed via a date scan operation, to take a sample of the functional data entering and leaving the IC. This instruction is also used to preload test data into the boundary-scan register before loading an EXTEST instruction.
31(MSB) 28 27 12 11 1 0(LSB) Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit) 0X0 0X33 1 JTAG DEVICE IDENTIFICATION REGISTER
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types) of an IC to a disabled (high-impedance) state and selects the one-bit bypass register to be connected between TDI and TDO. During this instruction, data can be shifted through the bypass register from TDI to TDO without affecting the condition of the IC outputs.
BYPASS The required BYPASS instruction allows the IC to remain in a normal functional mode and selects the one-bit bypass register to be connected between TDI and TDO. The BYPASS instruction allows serial data to be transferred through the IC from TDI to TDO without affecting the operation of the IC.
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IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tTCK t4 t1
TCK
t2
t3
TDI/ TMS
tDS
TDO
tDH
TDO
t6
TRST
Notes to diagram: t1 = tTCKLOW t2 = tTCKHIGH t3 = tTCKFALL t4 = tTCKRISE t5 = tRST (reset pulse width) t6 = tRSR (reset recovery)
tDO
5904 drw38
t5
Figure 35. Standard JTAG Timing
JTAG AC ELECTRICAL CHARACTERISTICS
(vcc = 3.3V 5%; Tcase = 0C to +85C)
Parameter Symbol Test Conditions Min. Max. Units 5
(1)
SYSTEM INTERFACE PARAMETERS
IDT72V51546 IDT72V51556 Parameter Data Output Data Output Hold Data Input Symbol tDO(1) tDOH(1) tDS tDH trise=3ns tfall=3ns Test Conditions Min. 0
10 10
JTAG Clock Input Period tTCK JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery
NOTE: 1. Guaranteed by design.
-
100 40 40 50 50
ns ns ns ns ns ns ns
tTCKHIGH tTCKLOW tTCKRISE tTCKFALL tRST tRSR
Max. Units 20 -
ns ns ns
5(1) -
NOTE: 1. 50pf loading on external output signals.
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ORDERING INFORMATION
IDT XXXXX Device Type X Power XX Speed X Package X Process / Temperature Range BLANK I(1) BB 6 7-5 L 72V51546 72V51556 Commercial (0C to +70C) Industrial (-40C to +85C) Plastic Ball Grid Array (PBGA, BB256-1) Commercial Only Commercial and Industrial Low Power 1,179,648 bits 3.3V Multi-Queue Flow-Control Device 2,359,296 bits 3.3V Multi-Queue Flow-Control Device
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Clock Cycle Time (tCLK) Speed in Nanoseconds
NOTE: 1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades available by special order.
DATASHEET DOCUMENT HISTORY
10/12/2001 11/16/2001 12/19/2001 01/15/2002 04/05/2002 07/01/2002 06/04/2003 pgs. 1, 8, 11, 15, 16 and 29. pgs. 4, 11, 17-19, 23-25, 29-32, 34, 47 and 48. pgs. 13 and 30. pg. 52. pgs. 7, 8, 10, 11, 14, 48 and 53. pgs. 2, 7-12 and 29. pgs. 1 through 58. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
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for Tech Support: 408-330-1533 email: Flow-Controlhelp@idt.com

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